Verilog-2001 parameter declarations

[Mark Lancaster]

I'm trying to use Verilog-2001 style module port declarations and have
a parameter defined as well. See my example:

module my_module (
output [WIDTH-1:0] my_output,
input [WIDTH-1:0] my_input
)

parameter WIDTH = 1;

assign my_output = my_input;

endmodule

I can't figure out where to put the parameter declaration to get rid
of the syntax errors that are being reported (using VCS 7.0). Can
parameters be declared when defining ports in this manner?

Thanks,
Mark

[VhdlCohen]

Here's how:
module my_module
#(parameter WIDTH = 8) // 0 -> full board, 1 -> 1 mem unit

(
output [WIDTH-1:0] my_output,
input [WIDTH-1:0] my_input

);

assign my_output = my_input;

endmodule // my_module

// For instantiation:
my_module
#(.WIDTH (8))
my_module1
( // output
.my_output (data_out[7:0]),
.my_input (data_in[7:0])
);
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

[John_H]

From page 7 of the "Verilog HDL Quick Reference Guide" from
www.sutherland-hdl.com, one of the valid declaration forms may be as
follows:

module my_module #( parameter WIDTH = 1 )

( output [WIDTH-1:0] my_output,
input [WIDTH-1:0] my_input

);

assign my_output = my_input;

endmodule

This appears to work fine with the Synplify implementation of Verilog-2001.

"Mark Lancaster" <mark.la...@motorola.com> wrote in message
news:3F268E73...@motorola.com...

[Eliot Franklin]

It seems that the ANSI C port definition can't handle when all the
parameters are defined in an include file. For example:

module mymod (mybus);
`include "def.v" // defines BUS_WIDTH
input [BUS_WIDTH:0] mybus;
...

You can't use the ANSI C ports, because the include file doesn't get
included until after the portlist.

This seems like a big limitation of ANSI C style ports.

Eliot

"John_H" <johnha...@mail.com> wrote in message news:<YFAVa.26$tC....@news-west.eli.net>...

[VhdlCohen]

>It seems that the ANSI C port definition can't handle when all the
>parameters are defined in an include file. For example:
>
>module mymod (mybus);
>`include "def.v" // defines BUS_WIDTH
>input [BUS_WIDTH:0] mybus;
>...
>
>You can't use the ANSI C ports, because the include file doesn't get
>included until after the portlist.
>
>This seems like a big limitation of ANSI C style ports.
>
>Eliot

Not true. Below is a cutout of a modeld that worked:
Notice a mixture of parameters + `include.
module mem_slave
#(parameter number_idtmem = 0,
`include "ahb_param.v"

) // 0 -> full board, 1 -> 1 mem unit
(

output [31:0] hrdata, // Slave Read data bus
...

[Steven Sharp]

eliot.f...@conexant.com (Eliot Franklin) wrote in message news:<22e263df.03082...@posting.google.com>...

> It seems that the ANSI C port definition can't handle when all the
> parameters are defined in an include file. For example:
>
> module mymod (mybus);
> `include "def.v" // defines BUS_WIDTH
> input [BUS_WIDTH:0] mybus;
> ...
>
> You can't use the ANSI C ports, because the include file doesn't get
> included until after the portlist.
>
> This seems like a big limitation of ANSI C style ports.

There is nothing preventing you from putting the contents of an ANSI-C
style parameter list in an include file, and including them at the
appropriate place in the declaration:

module mymod #(

`include "def.v" // defines BUS_WIDTH

) (input [BUS_WIDTH:0] my_bus);

This is a little ugly because of the requirement for `include to be
on its own line, but it is perfectly legal syntax.

You would have to make the contents of the file match the syntax of an
ANSI-C style parameter list instead of old-style parameter declarations,
but that should be fine if you are using ANSI-C style everywhere.

[Eliot Franklin]

Thanks for the replies.

This would work great, however it looks like VCS 7.0 +v2k can't
compile the parameter syntax "module modname #(parameter_list)". So
I'll have to wait until it gets supported by VCS.

Eliot

[VhdlCohen]

>
>This would work great, however it looks like VCS 7.0 +v2k can't
>compile the parameter syntax "module modname #(parameter_list)". So
>I'll have to wait until it gets supported by VCS.
>
>Eliot

Tha's what "NICE" about a "supported" standard!
Checkout "The IEEE Verilog-2001 Simulation Tool Scoreboard" at
http://www.sunburst-design.com/papers/
:)
Ben