Verilog Warnings

[lllaura]

Hello! I'm running a verilog program where I declare 5 wires inside the
module. I keep getting a
WARNING:Implicit wire has no fanin
I don't think that this is bad. Am I wrong? If it isn't bad, can you tell
me how I can turn it off? It's really getting in my way!

Thank you,
Laura Lucas

[Xanatos]

I'd have to see the code of the "Implicit wire" to see if its bad so to
speak.

What simulator are you using? Perhaps if you run it with the -w flag (turn
off warnings on some sims) it will get rid of that message.

Cheers,
Xanatos

[igla...@my-deja.com]

Hi,

The warning try to tell you that this wire is not driven by
anything, it is just "stay in the air"

for example let say you have a AND gate with 2 input and one of the
input called in1 have a wire that is not connected.

the point of is it bad or not, is depend on does this wire need to do
something but I would recommend you check in your logic and if this
wire not need to be there just remove it, most likely if it is there
and you have this warning it mean you forgot to make some connection.

have a nice day

Illan

In article <ZASM4.5940$18.44...@news-east.usenetserver.com>,

"lllaura" <lll...@iname.com> wrote:
> Hello! I'm running a verilog program where I declare 5 wires inside
the
> module. I keep getting a
> WARNING:Implicit wire has no fanin
> I don't think that this is bad. Am I wrong? If it isn't bad, can
you tell
> me how I can turn it off? It's really getting in my way!
>
> Thank you,
> Laura Lucas
>
>

Sent via Deja.com http://www.deja.com/
Before you buy.

[lllaura]

Thank you for helping!

What my module is doing is checking to see if idx and issue_idx are the same
register number (this is done by calling number_nompare which returns a 1
bit output), and, if they are the same and if the issue_write_enable is
high, write the "information" (omitted here for simplicity).

issue_same is where it is saying WARNING: Implicit wire has no fanin
but I NEED it to drive the result from the Number_Compare to the "and".
And I call it about 300 times in my code leaving pages of warnings in my
output.

Here's my code (scaled down).

module write_control(idx, issue_idx, issue_write_enable, issue_data);
input[5:0] idx, issue_idx;
input issue_write_enable;
input[63:0] issue_data;

wire issue_same;
wire issue_wr_en;

number_compare equal_idx(.out(issue_same),
.in1(issue_idx),
.in2(idx));
and RB_is_enable(issue_wr_en,
issue_same,
issue_write_enable);

write_it writer(idx, issue_wr_en, issue_data);

endmodule // write_control

Is there a way around this?

Thank you,
Laura

BTW, I'm working on a UNIX platform.

[lllaura]

Thanks! The verilog -w *.v is a great temporary fix!

Xanatos <deletemeao...@hotmail.com> wrote in message
news:I__M4.143623$1C2.3...@news20.bellglobal.com...

> > Hello! I'm running a verilog program where I declare 5 wires inside the
> > module. I keep getting a

> > WARNING:Implicit wire has no fanin

> > I don't think that this is bad. Am I wrong? If it isn't bad, can you
> tell
> > me how I can turn it off? It's really getting in my way!
> >
> > Thank you,
> > Laura Lucas
> >

[Utku Ozcan]

Laura,

I am in the same opinion with Illan. Don't disable the warnings with
Verilog-XL options. This warning states a design failure. An input
somewhere in the design is not driven. If the warnings seem to be
related to issue_same, then your code number_compare has some
uncomplete Verilog modelling.

Utku

--
I feel better than James Brown.

[igla...@my-deja.com]

Hi,

According to what you write if I understand correct the
module "number_compare equal_idx" get two input make a compare between
them and the result is send out and this is the signal you have problem
with.

I would guess this module is somethink like:

assign out = (in1 == in2) ;

if so it should be ok.

BTW you call the second module "RB_is_enable" using position and not
sirect connection like you did in the first one and this is some waht
risky you might consider using always a implicit call (i.e .in1
(a1), .in2(a2) etc and not a1,a2 etc).

I also use Unix , not that it's matter :-)

have a nice day

Illan

In article <bP6N4.263$G7.2...@news-east.usenetserver.com>,