synthesis error with DC

rajan

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Aug 30, 2004, 1:24:38 PM8/30/04

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Hi,

I am trying to synthesize a design with synopsys. But, keep on getting this
error. Would anyone please make this erro message clear to me.

Warning: Design 'design_core' has '1' unresolved references. For more
detailed information, use the "link" command. (UID-341)
Information: Updating design information... (UID-85)
Allocating blocks in 'design_core'

Error: The selector S_18 is shorted to the selector S_2.
Resource sharing does not support operations that are
shorted together. (SR-8)
Error: Cannot load design 'design_core'. (DDB-76)
0

Jonathan Bromley

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Aug 31, 2004, 9:00:44 AM8/31/04

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On Mon, 30 Aug 2004 18:24:38 +0100, "rajan"
<rajan...@hotmail.com> wrote:

>I am trying to synthesize a design with synopsys. But, keep on getting this
>error. Would anyone please make this erro message clear to me.

It's two error messages, in fact...

>Warning: Design 'design_core' has '1' unresolved references. For more
>detailed information, use the "link" command. (UID-341)

You have an instance of a component that has not yet been
read into Synopsys, and isn't in its libraries.
Consequently, you will get a component-shaped hole in
the finished netlist. If the component in question is
a primitive that already exists in your target technology,
then this is probably OK. However, it's more likely that
you simply forgot to compile something.

>Error: The selector S_18 is shorted to the selector S_2.
> Resource sharing does not support operations that are
> shorted together. (SR-8)

I think this means that you are trying to give some register
a value from more than one always block, or you are trying to
give a wire its value from more than one assign statement.

>Error: Cannot load design 'design_core'. (DDB-76)

...because of the previous error.
--
Jonathan Bromley, Consultant

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Mike Treseler

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Aug 31, 2004, 2:07:14 PM8/31/04

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"rajan" wrote:
>
> Warning: Design 'design_core' has '1' unresolved references.

Consider simulation before synthesis
to correct logical errors.

-- Mike Treseler

Jonathan Bromley

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Sep 1, 2004, 4:24:04 AM9/1/04

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On 31 Aug 2004 11:07:14 -0700, mike_t...@comcast.net (Mike
Treseler) wrote:

>"rajan" wrote:
>>
>> Warning: Design 'design_core' has '1' unresolved references.
>
> Consider simulation before synthesis
> to correct logical errors.

It's possible there weren't any. If this was a Verilog
design in which a variable (reg) was written at different
times from two different "always" blocks, it could give
correct results in simulation but yet be unsynthesisable.
Similarly, most synthesis tools use different library
structures than simulation tools, so it's possible to miss
out a file from the synthesis run and get "unresolved
reference" errors even after a successful simulation.

Whilst I completely agree with your necessarily oft-repeated
exhortation, it doesn't deal with all the likely problems.

Metin Yerlikaya

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Sep 1, 2004, 5:41:05 PM9/1/04

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hi,
seems like a net has more than one driver. You can see schematic in
GTECH level(Design Analyzer),
and try to find the s_18 and s_2 blocks and may be you find which net
you are
trying to drive double.

Metin

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