Newbie NC Verilog Question

[Mike North]

I am trying to setup a parallel simulation run with NC Verilog and am having
trouble with the command line... I have been trying the basic command lines
of:
ncverilog test1.v +ncuid+ONE
ncverilog test2.v +ncuid+TWO
AND
ncverilog test1.v +nclibdirname+INCA_ONE_libs
ncverilog test2.v +nclibdirname+INCA_TWO_libs

which work BUT doesn't really reflect my situation....I'm having trouble
with feeding in a list of files and the parameters I was feeding to
ncvlog...the command line used to look like
ncvlog -f run_nc.vc(list of parameters, includes etc...) -f
run_source_list.vc(list of source files)
which did the job. I'm new to both Verilog & the NC Tools....any
suggestions...I've been RTFM'ing

[Parvathy Uma]

What kind of parallel simulation do you want to run?
If it is the same design (in other words , the same verilog code)
you can build a snapshot (ncvlog and ncelab) and then use that snapshot
to run multiple simulations with ncsim. The simulation runs can be on
different machines as long as they all run the same OS.

IMO running ncvlog/ncelab/ncsim is much better that running ncverilog.

-Uma

"Mike North" <mno...@catena.com> wrote in message news:<h0C37.11$D7...@news.on.tac.net>...

[Srinivasan Venkataramanan]

>===== Original Message From parvat...@hotmail.com (Parvathy Uma) =====
<SNIP>

>IMO running ncvlog/ncelab/ncsim is much better that running ncverilog.
>

I too agree with this, but in general this concept of
compile-elaborate-simulate is easier for VHDL guys to digest than pure
Verilog
people. Infact I remember reading somewhere that one gets the maximum
performance benefit from NC by using ncvlog-ncelab-ncsim approach than
ncverilog.

Srini

ASIC Design Engineer
Chennai (Madras), India