always vs assign
Jordan Dimitrov
Again I have a fundamental, or at least I think it's fundamental,
question. What is the difference between
assign wire = exp;
and
always @(v1 or v2 or ... or vN) wire = exp,
where v1, v2, ..., vN are exp's variables? I am asking this question
not because I don't know if there is any difference between those two
constructs, clearly there are well known examples that show it. My
problem is that I don't understand it.
Any input is welcome.
--
============
Jordan
http://www.cse.dmu.ac.uk/~jordan/
Sudhir Kadkade
You must already know that procedural assigments cannot be
made to wires, so I will assume that in the second piece of
code the type of 'wire' is reg.
That said, there is no semantic difference in the way you have
used the continuous assignment and the procedural assignment.
In fact they should synthesize identically - either a latch or some
combinational logic driving 'wire'.
Assuming this is what you wanted, you may care that some
simulators levelize the continuous assignment evaluation when
they can. In these simulators, the levelized continuous
assignment is evaluated only once, whereas the procedural
assignment may be evaluated more than once. I have not yet
encountered a simulator that levelized procedural assignments.
If you wanted the latch or combinational logic. I would decide
which construct to use based on the other features available
in continuous assignments vs. procedural assignments.
These are delays and strengths. You can give strengths to
wires and not regs (so you would use the continuous
assignment if you wanted this feature). The delay semantics
for a continuous assignment and a procedural assignment are
very different (see the IEEE1364-1995 spec).
Regards,
Sudhir
Jordan Dimitrov wrote in message <7ppupdw...@strl.dmu.ac.uk>...
taniwha
>
> Dear all,
>
> Again I have a fundamental, or at least I think it's fundamental,
> question. What is the difference between
>
> assign wire = exp;
>
> and
>
> always @(v1 or v2 or ... or vN) wire = exp,
>
> where v1, v2, ..., vN are exp's variables? I am asking this question
> not because I don't know if there is any difference between those two
> constructs, clearly there are well known examples that show it. My
> problem is that I don't understand it.
actually it's a great question - possible one of the questions most
asked
by people new to Verilog.
Basicly the simple answer is that they are almost the same - you use the
always form when you want to write to something declared as a 'reg'
and the assign form when you want to write to something declared as a
'wire'.
Often you use the second form and declare something you would normally
naturally declare as a 'wire' as a 'reg' when you'd like to use
something
much more complex that 'wire=exp' - perhaps the guts of a state machine
using case statements, if statements, temporary variables etc
In draft 2 (not available in most simulators) you can also avoid all the
v1 or v2 or .... vN and just say:
always @(*)
wire = exp;
and the compiler will figure it out for you - not being widely
implemented
means that this construct is not portable yet so don't go wild.
Paul Campbell
pa...@verifarm.com
glen herrmannsfeldt
> What is the difference between
> assign wire = exp;
>and
> always @(v1 or v2 or ... or vN) wire = exp,
>where v1, v2, ..., vN are exp's variables? I am asking this question
>not because I don't know if there is any difference between those two
>constructs, clearly there are well known examples that show it. My
>problem is that I don't understand it.
I don't know the real answer, so I will tell you how I know it.
Nodes called 'wire' should be driven by a continuous assignment, which
is like connecting a wire to the output of a device. The assign statement
identifies the source of the signal for that wire. This is structural
model coding.
Nodes called 'reg' have a memory of what was done to them last. I tend
to imagine that they have a large capacitor attached so that they will
keep the last voltage that they were given. This voltage can be changed
by executing wire = value statement. This is behavioral model coding.
Structural model is easier to use for logic synthesis. It maps
directly to the connect this gate to that gate that one normally
considers as logic design.
Behavioral model is more like a programming language, in that statements
are executed in order. It is more like a multithreaded language, where
multiple threads of execution may occur, though each thread executes
sequentially.
Note that assign statements are not executed, but describe a condition
that is true throughout the verilog code.
Registers and latches can normally only be written in always blocks,
so synthesis tools know how to recognize them. They may or may not
be able to synthesize from other behavioral model code, but should be
able to from all structural logic code.
Someone can comment if this doesn't follow the letter of the standard.
It works for me, and I think it gets the idea across at least as well.
-- glen
Jordan Dimitrov
Thank you for your response. I had to be a bit more specific in the
first post. Of course wire in the second construct is of type reg. In
fact I could give even a complete Verilog example like the modules
Nand1 and Nand2 below.
module Nand1(i0,i1,o);
input i0,i1;
output o;
assign o = ~(i0 & i1);
endmodule // Nand1
module Nand2(i0,i1,o);
input i0,i1;
output o; reg o;
always @(i0 or i1) o = ~(i0 & i1);
endmodule // Nand2
From what all of you have pointed out, I can draw the conclusion that
those modules are interchangeable, aren't they?
igla...@my-deja.com
There is one small additional issue about assign VS always and that
is to do with how the compiler react to assign in compre to always,
meanign that one he do and "forget" and the other he might redo few
times (or again and again) for the same tick time.
assume you have 2 modules A and B
and assume modlue A have an output signal name ao go to module B as
input
and assume modlue B have an output signal name bo go to module A as
input
now assume than ao is a function of bo and bo is a function of ao.
lastly assume that any change in ao will make a change in bo and vice
versa something like SR circuit.
if you sample those signal than all will go well but if you don't than
there is a big differance, the always will actually cause an infinite
loop.
of course you might want to redesign or recode your design so such a
senario will not happen and that's fine, however long ago I was part of
a group designing a large Asic and 2 people designed 2 different
modules with some handshake and non was aware of what the other did and
when integrating there module we got this infinite loop.
have a nice day
Illan
In article <394E85E8...@taniwha.com>,
taniwha <tan...@taniwha.com> wrote:
> Jordan Dimitrov wrote:
> >
> > Dear all,
> >
> > Again I have a fundamental, or at least I think it's fundamental,
> > question. What is the difference between
> >
> > assign wire = exp;
> >
> > and
> >
> > always @(v1 or v2 or ... or vN) wire = exp,
> >
> > where v1, v2, ..., vN are exp's variables? I am asking this question
> > not because I don't know if there is any difference between those
two
> > constructs, clearly there are well known examples that show it. My
> > problem is that I don't understand it.
>
> actually it's a great question - possible one of the questions most
> asked
> by people new to Verilog.
>
> Basicly the simple answer is that they are almost the same - you use
the
> always form when you want to write to something declared as a 'reg'
> and the assign form when you want to write to something declared as a
> 'wire'.
>
> Often you use the second form and declare something you would normally
> naturally declare as a 'wire' as a 'reg' when you'd like to use
> something
> much more complex that 'wire=exp' - perhaps the guts of a state
machine
> using case statements, if statements, temporary variables etc
>
> In draft 2 (not available in most simulators) you can also avoid all
the
> v1 or v2 or .... vN and just say:
>
> always @(*)
> wire = exp;
>
> and the compiler will figure it out for you - not being widely
> implemented
> means that this construct is not portable yet so don't go wild.
>
> Paul Campbell
> pa...@verifarm.com
>
Sent via Deja.com http://www.deja.com/
Before you buy.
Utku Ozcan
>
> Again I have a fundamental, or at least I think it's fundamental,
> question. What is the difference between
>
> assign wire = exp;
>
> and
>
> always @(v1 or v2 or ... or vN) wire = exp,
>
> where v1, v2, ..., vN are exp's variables? I am asking this question
> not because I don't know if there is any difference between those two
> constructs, clearly there are well known examples that show it. My
> problem is that I don't understand it.
>
Jordan,
another difference is, although both can represent the same
model, some simulators simulate one of them faster than the
other. For example, Verilog-XL Simulator simulates "wire="
expression faster than "always". This is an environmental
difference. If you have very long simulation, this might play
a role. There can also be cases for synthesizers. Please
check the manuals of your tools for details.
Utku
--
I feel better than James Brown.
taniwha
>
> Hi,
>
> There is one small additional issue about assign VS always and that
> is to do with how the compiler react to assign in compre to always,
> meanign that one he do and "forget" and the other he might redo few
> times (or again and again) for the same tick time.
>
> assume you have 2 modules A and B
>
> and assume modlue A have an output signal name ao go to module B as
> input
>
> and assume modlue B have an output signal name bo go to module A as
> input
>
> now assume than ao is a function of bo and bo is a function of ao.
>
> lastly assume that any change in ao will make a change in bo and vice
> versa something like SR circuit.
>
> if you sample those signal than all will go well but if you don't than
> there is a big differance, the always will actually cause an infinite
> loop.
actually I've seen 0-time loops like these happen with both assigns and
always statements.
Circuits like these seldom happen in the real world - but they do (I
remember the day the guy from physical group extracted his ring
oscilator
and added it to the logic simulation ..... of course real world ring
oscilators have real-world delays in them, raw extracted ones often
look like a simple delayless netlist :-)
Paul Campbell
Jeffrey Turner
> Dear all,
>
> Thank you for your response. I had to be a bit more specific in the
> first post. Of course wire in the second construct is of type reg. In
> fact I could give even a complete Verilog example like the modules
> Nand1 and Nand2 below.
>
> module Nand1(i0,i1,o);
> input i0,i1;
> output o;
>
> assign o = ~(i0 & i1);
> endmodule // Nand1
>
> module Nand2(i0,i1,o);
> input i0,i1;
> output o; reg o;
>
> always @(i0 or i1) o = ~(i0 & i1);
> endmodule // Nand2
>
> From what all of you have pointed out, I can draw the conclusion that
> those modules are interchangeable, aren't they?
AFAIK, they are the same. They are both purely imaginary in that there
are no delays and anyone who designs a "real world" circuit would, I
would hope, never have to code at this level. Also there are built-in
nand gates in verilog if for some reason you had to get down to the gate
level, so there's no point in reinventing the wheel. It's a purely
academic exercise - unfortuneately far too common among academics and
texts to give these sorts of examples which are of no use at all. I
can't understand how VHDL has the academic association and verilog the
"real world" when verilog texts so commonly code like this piece of
useless, academic, junk. Plunk, plunk - my two cents.
--Jeff Turner
Ajay
Not if more than one variables v1 or v2 or ... vN change simulatanously.
Then there's a race between the triggering statements and the body
of always block, and there's a possiblity of wire ending up with
incorrect value. assign will not miss any changes in the exp.
-Ajay
Jordan Dimitrov wrote:
>
> Dear all,
>
> Again I have a fundamental, or at least I think it's fundamental,
> question. What is the difference between
>
> assign wire = exp;
>
> and
>
> always @(v1 or v2 or ... or vN) wire = exp,
>
> where v1, v2, ..., vN are exp's variables? I am asking this question
> not because I don't know if there is any difference between those two
> constructs, clearly there are well known examples that show it. My
> problem is that I don't understand it.
>
> Any input is welcome.
Paul Johnson
news:399C6C58...@synopsys.com...
> Jordan,
>
> Not if more than one variables v1 or v2 or ... vN change simulatanously.
> Then there's a race between the triggering statements and the body
> of always block, and there's a possiblity of wire ending up with
> incorrect value. assign will not miss any changes in the exp.
If I understand you correctly, you're saying that you can't use an always
for combinatorial logic, in case more than one input changes at the same
time. Surely this isn't right?
> Jordan Dimitrov wrote:
> >
> > Dear all,
> >
> > Again I have a fundamental, or at least I think it's fundamental,
> > question. What is the difference between
> >
> > assign wire = exp;
> >
> > and
> >
> > always @(v1 or v2 or ... or vN) wire = exp,
> >
> > where v1, v2, ..., vN are exp's variables? I am asking this question
> > not because I don't know if there is any difference between those two
> > constructs, clearly there are well known examples that show it.
Can you post an example to show the difference?
Thanks
Paul
Shalom Bresticker
That is not right.
Shalom Bresticker
Paul Johnson wrote:
--
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Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
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Muhammad Nasiri