problem simulating with SDF
Chris Briggs
development flattened netlist and the SDF file and I'm trying to run a
simulation with it, but having trouble using it with NC-Verilog
v3.4.(s012).
I added $sdf_annotate("gluttony.sdf", i_gluttony); to the testbench
and got these errors when I ran it:
---- start here ----
ncsdfc: *E,SDFIRE: "/engim/projects/gluttony/ibm_postfep/gluttony.sdf",
line 18: Syntax error ":1".
ncelab: *W,SDFCNC: Cannot compile SDF file,
/engim/projects/gluttony/ibm_postfep/gluttony.sdf - skipping
annotation.
---- end here ----
The SDF file starts with this:
/*****************************************************************
Current Compressed: OFF
Delay Mode: CURRENT
Delay Detail: INTERCONNECT & CELL DELAY SEGMENTS
Pin Prefix Control: OFF
Primary Delay Segment Control: TRUE
Timing Check: ON
Type of Delay Records: AUSSIM
*****************************************************************/
( DELAYFILE
(SDFVERSION "2.1")
(DESIGN "gluttony" )
(DATE "06:18:42 on Friday, 25 October 2002" )
(VENDOR "IBM")
(PROGRAM "ITVsdf")
(VERSION "1.00" )
(DIVIDER : )
(VOLTAGE 1.60:1.50:1.37 )
(PROCESS "best:nominal:worst" )
(TEMPERATURE 0.00:25.00:110.00 )
(TIMESCALE 1 ns )
(CELL (CELLTYPE "gluttony" )
(INSTANCE )
(DELAY
(ABSOLUTE
(INTERCONNECT agc0_0_ PAD_agc0\[0\]:PAD ( 0.004 ) ( 0.004
) )
It seems to be getting screwed up by the (DIVIDER : ) line, but I'm
not an expert so you tell me. Anyway, I commented out the VOLTAGE and
TEMPERATURE lines, since I understand them to be just informational,
and now I get lots of errors like these:
---- start here ----
ncelab: *W,SDFINF: Instance BUFFOPT6_ISCAN_NET_475.1 not found at
scope level <top-level>.
ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path
(IOPATH D0 Z) of instance zzz_tb.i_gluttony.u_chip_arc_jtag_mux of
module MUX21_E.
---- end here ----
But these instances and paths do exist. This first is a wire declared
as:
wire \BUFFOPT6_ISCAN_NET_475.1 ;
And the second:
MUX21_E u_chip_arc_jtag_mux(
.D0(arc_tdo_o),
.D1(chip_tdo_o),
.SD(jtag_select_only_mux_Z),
.Z(tdo_o)
);
I found in the docs that the SDF annotator is supposed to
automatically convert to escaped Verilog names, so I don't understand
why they aren't matching up.
Looking throught the docs, I came across something that said normally
a period or slash is used as the hierarchical separator, so I wrote a
quick perl script to convert all the colons to slashes, changed the
DIVIDER line, and tried again. But then I got a different set of
SDFINF and SDFNEP errors.
Obviously I'm just guessing and I figure they must be other folks
who've used IBM and NC and done this. So can anyone tell me how to
make this work?
TIA
-cb
Jon Beniston
> Obviously I'm just guessing and I figure they must be other folks
> who've used IBM and NC and done this. So can anyone tell me how to
> make this work?
Have you not tried talking to someone from IBM?
> TIA
>
> -cb
David J. Roberts
> ---- start here ----
> ncsdfc: *E,SDFIRE: "/engim/projects/gluttony/ibm_postfep/gluttony.sdf",
> line 18: Syntax error ":1".
> ncelab: *W,SDFCNC: Cannot compile SDF file,
> /engim/projects/gluttony/ibm_postfep/gluttony.sdf - skipping
> annotation.
> ---- end here ----
>
/* snip snip snip */
> Type of Delay Records: AUSSIM
> *****************************************************************/
> ( DELAYFILE
> (SDFVERSION "2.1")
> (DESIGN "gluttony" )
> (DATE "06:18:42 on Friday, 25 October 2002" )
> (VENDOR "IBM")
> (PROGRAM "ITVsdf")
> (VERSION "1.00" )
> (DIVIDER : )
The argument to divider can only be a "." or "/". You are telling the
SDF parser what character is used to break up the hierarchical names
in the SDF file.
> (VOLTAGE 1.60:1.50:1.37 )
> (PROCESS "best:nominal:worst" )
> (TEMPERATURE 0.00:25.00:110.00 )
> (TIMESCALE 1 ns )
> (CELL (CELLTYPE "gluttony" )
> (INSTANCE )
> (DELAY
> (ABSOLUTE
> (INTERCONNECT agc0_0_ PAD_agc0\[0\]:PAD ( 0.004 ) ( 0.004
> ) )
>
> It seems to be getting screwed up by the (DIVIDER : ) line, but I'm
> not an expert so you tell me. Anyway, I commented out the VOLTAGE and
> TEMPERATURE lines, since I understand them to be just informational,
> and now I get lots of errors like these:
>
> ---- start here ----
> ncelab: *W,SDFINF: Instance BUFFOPT6_ISCAN_NET_475.1 not found at
> scope level <top-level>.
> ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path
> (IOPATH D0 Z) of instance zzz_tb.i_gluttony.u_chip_arc_jtag_mux of
> module MUX21_E.
> ---- end here ----
>
> But these instances and paths do exist. This first is a wire declared
> as:
> wire \BUFFOPT6_ISCAN_NET_475.1 ;
NOTE: This is not an instance it's a wire. Therefore the instance path
does not exist.
>
> And the second:
> MUX21_E u_chip_arc_jtag_mux(
> .D0(arc_tdo_o),
> .D1(chip_tdo_o),
> .SD(jtag_select_only_mux_Z),
> .Z(tdo_o)
> );
>
> I found in the docs that the SDF annotator is supposed to
> automatically convert to escaped Verilog names, so I don't understand
> why they aren't matching up.
It automatically converts escaped SDF names to escaped Verilog names.
Chris Briggs
> Have you not tried talking to someone from IBM?
We're working with a consultant who's acting as a middleman between
IBM and us. And yes, I have been in touch with him as he's the one who
generated the file with EinsTimer. However, he doesn't have any
experience with simulating SDF, having told me that only one of his
previous clients has ever asked for it.
I've also gotten in touch with our local Cadence support. Basically,
I'm just throwing this out to everyone who might be able to help me.
Today I got the consultant to generate a new SDF file using / as the
divider, but it's not working either. If anyone know the magic
EinsTimer switch to generate this file so that it works with NC, let
me know and I'll pass it on.
-cb
Chris Briggs
> ch...@engim.com (Chris Briggs) writes:
> The argument to divider can only be a "." or "/". You are telling the
> SDF parser what character is used to break up the hierarchical names
> in the SDF file.
Right, I've gotten a new version with slash as the divider. I have no
idea why he used colon. Some other IBM tool likes it?
> > But these instances and paths do exist. This first is a wire declared
> > as:
> > wire \BUFFOPT6_ISCAN_NET_475.1 ;
> NOTE: This is not an instance it's a wire. Therefore the instance path
> does not exist.
Good point. Any idea why would the SDF file would have it as an
instance?
> It automatically converts escaped SDF names to escaped Verilog names.
Right, I saw that in the docs, but things still don't seem to match
up. Of course, if it's somehow got instances and wires backwards, that
would explain the errors, just not why it's wrong.
Anyway, as I said I got a new version with slash as the divider and I
still get SDFINF (instance not found) errors for wires and SDFNEP
(non-existent path) errors for module input-output paths. I think I
have to make our consultant reread his docs on generating SDF files,
unless someone here knows the magic switch to EinsTimer to fix this.
Thanks.
-cb
John Eaton
: ---- start here ----
: ncelab: *W,SDFINF: Instance BUFFOPT6_ISCAN_NET_475.1 not found at
: scope level <top-level>.
: ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path
: (IOPATH D0 Z) of instance zzz_tb.i_gluttony.u_chip_arc_jtag_mux of
: module MUX21_E.
: ---- end here ----
: But these instances and paths do exist. This first is a wire declared
: as:
: wire \BUFFOPT6_ISCAN_NET_475.1 ;
: And the second:
: MUX21_E u_chip_arc_jtag_mux(
: .D0(arc_tdo_o),
: .D1(chip_tdo_o),
: .SD(jtag_select_only_mux_Z),
: .Z(tdo_o)
: );
Somewhere you have a verilog lib with a module called MUX21_E.
Make sure that module has something that looks like:
specify
(DO => Z) = (0.010,0.010);
endspecify
John Eaton