Include file extension: ".v" vs ".vh"?
Andreas Ehliar
`include files. Although Verilog doesn't care about the
extension name at all I'm wondering what people in this
group prefer.
Is it common to use ".vh"? I've only seen it in a couple
of places, whereas I've seen ".v" in lots of designs at
for example opencores.
/Andreas
gabor
For me it depends on what's in the file I'm including.
I hadn't seen the .vh convention, but I use .v when
there is behavioral code in the file, mostly to convice
the editor to properly format and keyword highlight, etc.
When the file is only `define etc. I usually use a .inc
(include) file extension. This helps recognize the
file as something that is not compilable by itself.
Mostly I try not to use `include if I can avoid it.
Regards,
Gabor
Edmond Coté
I have typically used .v
FYI, SystemVerilog supports packages that can be loaded with the
import keyword, much like a C++ namespace. Depending on which tools
you have access to, you may want to check that out.
Edmond
unfrostedpoptart
> I've seen both ".v" and ".vh" used as extensions for
> `include files. Although Verilog doesn't care about the
> extension name at all I'm wondering what people in this
> group prefer.
I've seen .vh used for Verilog header files, containing `defines, and
`included in other .v files.
David
Petter Gustad
> Mostly I try not to use `include if I can avoid it.
Ditto.
Petter
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