Instantiating An Array In Verilog
Kevin T. Mortimer
I'm having some difficulty figuring out how to instantiate a 2-dimensional
array of registers. If anyone could help me out or point me to a design
tutorial, I would be very greatful....
Thanks,
Kevin Mortimer
________________________________________________________________________________
Kevin Mortimer
mor...@rpi.edu
jefftu...@my-deja.com
"Kevin T. Mortimer" <mor...@rpi.edu> wrote:
>
> I'm having some difficulty figuring out how to instantiate a 2-dimensional
> array of registers. If anyone could help me out or point me to a design
> tutorial, I would be very greatful....
Technically, you can't. You can have a one-dimensional array of
registers, of any size, but you can't have a two-dimensional array.
That's a pretty odd sounding architecture anyway, but if you declare
a register_set as an array of registers, you might make an array of
register_sets. That's it in a nutshell. Try:
reg [31:0] register_set[15:0]; // An array of 16 registers each
// 32 bits wide.
reg register_set[7:0]; // An array of 8 register_sets.
And I can't even guarantee that that will work. You just may
have to do this:
reg [31:0] register_set0[15:0];
reg [31:0] register_set1[15:0];
...
I'm pretty new to verilog myself (I don't think VHDL is any
less restrictive in this area). So I'm not sure the first
way will work. But I know the second will. You'll just
have to track the (I presume) interrupt/priority level elsewhere
and choose among the r_s0, r_s1, by more hands-on means.
That's ok, hardware access of a two-dimensional array is
hard to implement anyway.
One other suggestion. Try:
`define REGISTER reg[31:0];
`define REGISTER_SET reg[1023:0];
reg REGISTER_SET REG_ARRAY[31:0]; // This will give an array
// of 32 REGISTER_SETs.
and you could access any of the 32 memory contiguous REGISTERs
in a REGISTER_SET by indexing into it in steps of 32, that is
REGISTER regXY would be REG_ARRAY[X + 32 * Y]. Can you say
kludge? Knew ya could.
--Jeff Turner '82
"Let's Go Red" - they dissed us by leaving Tute out of the
NCAA Tourney. BTW. that's BS Physics '82. And digital
logic was still at the LSI scale, maybe. The year before
they had tubes in the electronics texts and digital was all
TTL. The debate was whether to achieve high data rates by
improving the production process for GaAs or deliver a power
plant with every high-speed product to power the ECL, even
15 years ago when I was in RF (up to a MAXIMUM of 4GHz, when
you needed microwave engineers with wave guides, etc. Did
anyone foresee 1GHz digital clock rates, no.
Sent via Deja.com http://www.deja.com/
Before you buy.
igla...@my-deja.com
A 2 dimention is simple
reg [width-1:0] name_of_array [depth-1:0] ;
this give you a depth register each size of width.
and this will be synthesizable.
two thing tho' you might want to consider :
1. a 2 dimention as above will not be "seen" in the waves so you might
want to have some "dummy signal" from this array.
2. to get to a certain bit you will need to have some sort of temp reg,
menaing that in the regular declarion of a reg like reg [7:0] a , you
can accsees bit 0 of a using a[0] .
however in 2 dimention you will need something like a[0][0] and this is
not supported, so you will have to have another reg like reg [width-
1:0] temp and let this temp be name_of_array[0] and than you can access
bit 0 by temp[0].
have a nice day
Illan
In article <8esu39$2da$1...@nnrp1.deja.com>,
jefftu...@my-deja.com wrote:
> In article <Pine.A41.3.96.1000504163737.12910C-100000@vcmr-
Rabindra Guha
> two thing tho' you might want to consider :
>
> 1. a 2 dimention as above will not be "seen" in the waves so you might
> want to have some "dummy signal" from this array.
special pragmas.
--
Rabindra Guha empowerTel Networks, Inc.
Sr. Design Engineer 2345 N. First St.,
gu...@empowertel.com San Jose, CA 95131.
Direct: (408)519-4540 Main: (408)519-4500 Fax: (408)519-4596 eFax:
(253)276-9223
sdfsdf
>
> reg [width-1:0] name_of_array [depth-1:0] ;
Note that this instantiation works fine for regs, but for some reason
does *not* work for wires. SIGH...
Does anyone know how to declare 2-D wires in verilog?
Steve Wilson
Think about what you are asking - a reg data type is equivalent to a
programming variable in other languages. A wire is merely a connection.
Since "arrays" normally store data, a two-dimensional wire structure
doesn't
make a great deal of sense.
Steve
Mark Curry
Au contraire!! The lack of a multi-dimensional "wire", and support
for multi-dimensional regs is one of the biggest shortcomings
in verilog IMHO.
And the problem came about because the designers of the language
were only thinking of arrays in terms of memories. Think
of it - not all regs end up being flip flips correct?
An example:
reg [ 31:0 ] many_results [ 0 : 7 ];
reg [2:0] select;
wire [ 31:0 ] y = many_results[ select ];
many_results is driven by strictly combinational logic
(not shown). This results in a very cleanly written mux.
Now, suppose one wishes to pass many_results from another module - hard
to do huh? Can't declare a multi-dimensional wire to hook
it up.
To see other multi-dimensional problems, try and
declare y as a reg, and produce the same results.
Ugly huh? Hint - what's the sensitivity list look
like?
There are many other examples of the need for true
multi-dimensional operations. I believe the new
verilog standard coming out is moving a step in the
right direction - but still drops the ball in some
areas IMHO.
Regards,
Mark
--
Mark Curry
mcu...@ti.cat.com
Remove the animal from the domain to reply.
Steve Wilson
I can't resist being just a bit of a smart-ass here.
How does "always @ *" strike you ;-)
Serioulsy - I agree only partially. I agree that multi-dimension
reg declarations would be a "good thing" but I'm not convinced that
the wires version makes sense. The thing I LIKE about verilog
is the fact that it is "closer" to hardware than my other choice in
an HDL. That "other" HDL doesn't have gate level primitives
for example.
As for moving ALL the contents of an array of any dimension to
another module - that isn't something I'd do in hardware nominally.
Hardware DOES have real physical restrictions after all. So I can
live without multi-dimension wires.
Steve
Shalom Bresticker
> Serioulsy - I agree only partially. I agree that multi-dimension
> reg declarations would be a "good thing" but I'm not convinced that
> the wires version makes sense. The thing I LIKE about verilog
> is the fact that it is "closer" to hardware than my other choice in
> an HDL. That "other" HDL doesn't have gate level primitives
> for example.
>
> As for moving ALL the contents of an array of any dimension to
> another module - that isn't something I'd do in hardware nominally.
> Hardware DOES have real physical restrictions after all. So I can
> live without multi-dimension wires.
>
> Steve
Anyway, IEEE 1364-2000 (Verilog 2000) DOES include multi-dimensional (not just 2-D) wires.
--
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Shalom Bresticker email: sha...@msil.sps.mot.com
Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
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