Time scale precision Vs Simulation time
Muthu
In verilog we are using `timescale 1ns/10ps. Meaning 1ns time unit
with 10ps precision.
My question is: will the simulation time will be affected with the
change in precision?
say if i give `timescale 1ns/100ps will the simulation time will be
less than the `timescale 1ns/10ps...
To my understanding, yeah there should be a simulation time
differences?
Actually how it will be???
Thanks in advance..
Best regards,
Muthu
Paulo Dutra
http://www.xilinx.com/techdocs/2224.htm
Basically, the smallest precision of all the timescale directive
determines the time precision.
--
/ 7\'7 Paulo Dutra (pa...@xilinx.com)
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Johnsonw10
> change in precision?
The answer is yes. Check out page 10 of the paper
http://www.sunburst-design.com/papers/CummingsICU1997_VerilogCodingEfficienc
y_rev1_1.pdf
HTH,
Jim
Steven Sharp
>
> The answer is yes. Check out page 10 of the paper
Perhaps it made a big difference in Verilog-XL, due
to the use of a time wheel or something similar.
However, I tried Cliff's toy example in NC-Verilog,
and there was no measurable effect, as I expected.
There is only one way that I can see the timescale
precision affecting simulation speed in NC-Verilog.
If a design contains a lot of different delays
specified to high precision, then different signals
will tend to change at different times from each
other. If the timescale precision is reduced, these
changes will be more likely to occur at the same
simulation time. E.g. two signals that would have
changed 1ps apart may now change at the same multiple
of 10ps. This reduces the overhead for handling more
different simulation times. This effect is more
often seen when doing SDF annotation with excessive
(and probably unwarranted) precision.