RTL vs. HDL
Vaseem Anjum
Can someone tell me the exact difference between RTL and HDL.
I've heard different interpretations. I'd like to hear your view.
Thanks,
Vaseem...
--
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Reply : vas...@berlioz.nsc.com
{decwrl,hplabs,sun,pyramid,amdahl}!berlioz.nsc.com!vaseem
Vaseem Anjum : National Semiconductor, MS D3677 Santa Clara 95052
Jwahar R. Bammi
>
> Can someone tell me the exact difference between RTL and HDL.
> I've heard different interpretations. I'd like to hear your view.
>
in my view, RTL is just another level of abstraction that your
HDL may or may not support. the way i view it, RTL is a convenient
abstraction of of the actual physical hardware, in which you model and
sequence the actual physical transfers that are possible in the
actual physical design in order to implement desired behaviors. these
transfers may or may not contain delays. from a modelling/simulation
point of view the key feature needed to support the RTL level of
abstraction is that all the transfers possible in a particular control
step occur simultaneously, ie: if you write
a <= b;
b <= a;
the values of `a' and `b' get exchanged. post 1.6 versions (and i
suspect OVI Verilog-HDL) of Verilog-HDL/Verilog-XL have support
RTL modeling that should be sufficient for most intents and purposes.
(the support for RTL is not as rich as in say N.mPC (or N.2) or other
isps like HDLs that were entirely designed around the RTL level of
abstraction)
cheers,
--
--
bang: uunet!cadence!bammi jwahar r. bammi
domain: ba...@cadence.com
GEnie: J.Bammi
CIS: 71515,155
Cindy Eisner
>
> Can someone tell me the exact difference between RTL and HDL.
> I've heard different interpretations. I'd like to hear your view.
>
HDL is just any Hardware Description Language, for instance, VHDL, Verilog, etc. RTL is
Register Transfer Level, and it is one of the levels of abstraction usually supported by
an HDL. other levels of abstraction are behavioral (sometimes called algorithmic) and gate
level.
in RTL, each register in the described hardware is declared and assigned, and a clock-by-
clock equivalence with the hardware can be seen even without explicitly coding delays. a
behavioral description, on the other hand, may not intend to a clock-by-clock equivalence to
the described hardware, and if it does, it may achieve the clock-by-clock equivalence using
delays the length of the clock period, for instance, in order to create a pulse, or by other
means than explicitly describing each register.
however, a lot of people use RTL to mean anything synthesizable, and behavioral to mean
all the rest, even if their behavioral is also technically RTL.
--
Cindy Eisner, Tel: 972-4-551551
CAD group, Fax: 972-4-551550
Zoran Microelectronics LTD, E-mail: ci...@Zoran.HellNet.Org
Advanced Technology Center
Haifa 31204, Israel
Elliot H. Mednick
> In article <1992Jun5.1...@berlioz.nsc.com>, vas...@berlioz.nsc.com> (Vaseem Anjum) writes:
> >
> > Can someone tell me the exact difference between RTL and HDL.
> > I've heard different interpretations. I'd like to hear your view.
>
> HDL is just any Hardware Description Language, for instance, VHDL, Verilog,> etc. RTL is
> Register Transfer Level, and it is one of the levels of abstraction usually> supported by
> an HDL. other levels of abstraction are behavioral (sometimes called> algorithmic) and gate
> level.
I think you misunderstood the question (not that it was phrased correctly).
In this case, RTL stands for Register Transfer Language. Before Verilog
and VHDL dominated the industry, there were a slew of so-called hardware
description languages, none of which were widely used and most were specific
to a certain level of abstraction. The subset of these which modeled
hardware at what we now call the register-transfer level were called
Register Transfer Languges. There was one RTL that almost became
a widely-used standard, but I forget its name (something like OCCAM(?)).
There were several papers presented in the mid 1970's on hardware description
languages and register transfer languages. If you are interested in the
references (for a historical perspective, perhaps?), it would not be too
difficult for me to dig them up.
--
Elliot H. Mednick P.O. Box 150
Wellspring Solutions Sutton, MA. 01590
ell...@Wellspring.com +1 508 865 7271
Eric Hughes
>I think you misunderstood the question (not that it was phrased correctly).
>In this case, RTL stands for Register Transfer Language. Before Verilog
>and VHDL dominated the industry, there were a slew of so-called hardware
>description languages, none of which were widely used and most were specific
>to a certain level of abstraction. The subset of these which modeled
>hardware at what we now call the register-transfer level were called
>Register Transfer Languges. There was one RTL that almost became
>a widely-used standard, but I forget its name (something like OCCAM(?)).
>--
>Elliot H. Mednick P.O. Box 150
>Wellspring Solutions Sutton, MA. 01590
>ell...@Wellspring.com +1 508 865 7271
OCCAM is the "machine language of transputers". Because of it's design,
it is occasionally used for other purposes.
I think the original HDL was DDL (Duley-Dietmeyer Language or Digital
Design Language, I think). It was presented in IEEE Trans. Comput.,
April, 1969. "HDL" doesn't seem to have a precise definition, so it's
best understood with it's purpose. For example, HDLs for simulation.
"RTL" is a more precise term.
Ed Taub
What is the recommended way to model a tri-state bus with multiple
devices hanging off of it in Verilog?
I want to simulate the bus idle state (nobody on bus) to be inactive
(0, not z), while allowing any single device's bidirectional I/O pin
to overrride the idle signal and place an active signal (1) on the
bus.
This must not cause a clash (x value) between the bus pull-down and
the active I/O pin. I've tried sensing the bus and quickly swappping
either z or 0 states into the "idle bus driver", but it not going
too well.
Thanks in advance.
Rob Warnock
+---------------
| What is the recommended way to model a tri-state bus with multiple
| devices hanging off of it in Verilog?
I've always used continuous assignments, for example:
wire [31:0] D_bus, my_D, his_D, other_guy_D;
wire my_oe, his_oe, other_guy_oe;
// connect several tri-state drivers to the bus
assign D_bus = my_oe ? my_D : 32'bz;
assign D_bus = his_oe ? his_D : 32'bz;
assign D_bus = other_guy_oe ? other_guy_D : 32'bz;
+---------------
| I want to simulate the bus idle state (nobody on bus) to be inactive
| (0, not z), while allowing any single device's bidirectional I/O pin
| to overrride the idle signal and place an active signal (1) on the bus.
+---------------
Change:
wire [31:0] D_bus;
to:
tri0 [31:0] D_bus;
in the outermost module containing "D_bus", only.
+---------------
| This must not cause a clash (x value) between the bus pull-down and
| the active I/O pin. I've tried sensing the bus and quickly swappping
| either z or 0 states into the "idle bus driver", but it not going too well.
+---------------
The "tri0" net type should do what you want.
-Rob
-----
Rob Warnock, MS-9U/510 rp...@sgi.com
Silicon Graphics, Inc. (415)390-1673
2011 N. Shoreline Blvd.
Mountain View, CA 94043
Gord Wait
Try the pulldown gates, with strength weak. If you don't declare it,
your tristate buffers are default strength strong, and will over-ride
the weak0 strength while driving. When all tristates are off, then the
weak will clear the bus for you.
untested example:
tri [7:0] databus;
pulldown (weak0) databus[7], databus[6], etc;
See sect 6 of the Cadence Verilog XL manual for more details (Version
1.6)
I don't know if this is allowed, but I doubt it:
pulldown (weak0) databus;
--
Gord Wait SMOS Systems Vancouver Design Centre
uunet!jericho!gord
jericho!go...@uunet.UU.NET
Brad Garton
>HDL is just any Hardware Description Language, for instance, VHDL,
Verilog, etc.
Cindy's answer is right, but VALID complicated things by calling their
SystemPLD
programmable logic design language 'HDL'. So HDL also means a specific design
language originally designed by Minc and resold by VALID and then resold by
CADENCE who bought VALID.
Hope this clears things up :-).
Brad
___________________________________________________________
| Brad Garton (512) 838-1333 | br...@titan.austin.ibm.com |
| I speak for myself not IBM | VNET: GARTON AT AUSTIN |
+---------------------------------------------------------+
Life is real?
leading company in an area of the country where I really want to live
due to my lack of knowledge about HDLs. The recruiter suggested that
with my background in digital design and software development that I'd
be a natural for learning and using HDLs. He said to do a crash course
on the subject, then call him back, and he'd set up an interview with
one of the company's more technical types. I'd really like that job!
What do I want from you? How about telling me which HDL is most popular
in industry today (doesn't matter which one I get started with because
the company has their own proprietary HDL anyway)? What public domain
HDL is available and where can I get a copy of the software? I think
there's a PD VHDL somewhere, but you'll have to feed me more info on
that one. How about suggesting some good books, tutorial type hopefully,
that I can go buy? Any other suggestions?????
Brian Dixon
di...@spot.colorado.edu
--
=============================================================
| Brian Dixon | "Fish to live, Live to fish!" |
| di...@spot.colorado.edu | (when my wife lets me...) |
=============================================================
Vaseem Anjum
Date: Fri, 5 Jun 92 10:43:18 PDT
From: sa...@hal.com (Bharat P. Savel)
To: vas...@berlioz.nsc.com
Subject: Re: RTL vs. HDL
Newsgroups: comp.lang.vhdl,comp.lang.verilog
Organization: HaL Computer Systems Inc.
Cc:
Status: RO
Content-Length: 733
X-Lines: 15
RTL is register transfer lang. typically these lang. can support very few
constructs (like register transfer-control branch, or a FSM).
HDL is a hardware desription lang. that supports more constructs. typically
this is used for behavioral desciption.
while this is a "philosophical" question, HDL's may include RTL (loosley), but
not the other way around. this is beacuse RTL is actually a lang. that
describes a hard. this interpretation has been dropped off late, as new
generation HDL's are more powerful than before
--
-------------------------------------------------------------------------------
Bharat P. Savel /tmp/Design_Engineer
Ext. 1057
Motto: If we can't fix it, it ain't broke
From sun!ztivax.zfe.siemens.de!a...@nsc.nsc.com Tue Jun 9 01:09:48 1992
Date: Tue, 9 Jun 92 09:53:11 +0200
From: a...@ztivax.zfe.siemens.de (Andreas Hohl)
To: vas...@berlioz.nsc.com
Subject: Re.: RTL/HDL
Content-Length: 1036
Status: RO
X-Lines: 26
Vaseem,
In general, HDLs can be classified as multi-level HDLs and HDLs dedicated
for a specific level of abstraction. Abstraction levels are defined by
models such as the Y-Chart model by Gajski and Kuhn. Following this
definition an RTL is an HDL which allows for a register transfer description
of a hardware system, but not for example for a system level description.
In practise, it is often hard to distinguish exactly between the various
level of abstraction and therefore the terms RTL and HDL are used as synonyms
in some cases. In the past, so called high-level HDLs, as VHDL, which cover
a range of abstraction levels (including RT) were depicted as RTL in contrast
to gate level descriptions (schematics or netlists).
Andreas Hohl
----------------------------------------------------
Andreas Hohl a...@zfe.siemens.de
ZFE BT SE 63, SIEMENS AG phone: (+49) 89-636-41895
Otto-Hahn-Ring 6 fax: (+49) 89-636-44950
8000 Munich 83
Germany
----------------------------------------------------
From sun!Lehigh.EDU!mk...@nsc.nsc.com Sat Jun 6 20:21:19 1992
Date: Sat, 6 Jun 92 23:01:28 EDT
From: mk...@Lehigh.EDU (Muhammad Khan Dhodhi)
Subject: Re: RTL vs. HDL
To: vas...@berlioz.nsc.com (Vaseem Anjum)
Content-Length: 726
Status: RO
X-Lines: 16
RTL VS HDL
By an HDL (Hardware Description Language) a digital design can be
described many levels of abstraction. ie.e gate level, register transfer
level (RTL), at algorithmic level. Further more it could be a behavioral
description or a structural description. e.g VHSIC Hardware Description
Language (VHDL) allows to describe a design at all levels of description.
Now RTL ( which stands for Register Transfer Level). At RTL level a digital
design is described in terms of a set of interconnected registers. Designer
have to specify what operation is being carried out in what clock cycle.
At RTL level still some Hardware description language (HDL) is used to
describe the design.
Muhammad K. Dhodhi
Lehigh University
From wellspring!Wellspring.COM!ell...@unixland.natick.ma.us Sat Jun 6 15:36:31 1992
Date: Sat, 06 Jun 1992 15:26:59 EDT
From: "Elliot H. Mednick" <@unixland.natick.ma.us:ell...@wellspring.com>
Organization: Wellspring Solutions
Reply-To: "Elliot H. Mednick" <@unixland.natick.ma.us:ell...@wellspring.com>
To: vas...@berlioz.nsc.com
Subject: Re: RTL vs. HDL
Content-Length: 756
Status: RO
X-Lines: 15
In article <1992Jun5.1...@berlioz.nsc.com> you write:
> Can someone tell me the exact difference between RTL and HDL.
> I've heard different interpretations. I'd like to hear your view.
HDL: Hardware Description Language - A simulation language used to
prototype and simulate hardware designs.
RTL: Register-Transfer Language (or Register-Transfer Level) Used
to model hardware at a specific level of detail; i.e. where storage
elements are known. As opposed to behavioral-level, architectural-level,
gate-level, etc.
--
Elliot H. Mednick P.O. Box 150
Wellspring Solutions Sutton, MA. 01590
ell...@Wellspring.com +1 508 865 7271
From sun!cup.portal.com!David_Bru...@nsc.nsc.com Fri Jun 5 22:59:52 1992
To: vas...@berlioz.nsc.com
From: David_Bru...@cup.portal.com
Subject: RTL versus HDL
Lines: 11
Date: Fri, 5 Jun 92 22:39:13 PDT
X-Origin: The Portal System (TM)
Content-Length: 745
Status: RO
X-Lines: 11
RTL stands for several things, Register Transfer Level and Resistor/
Transistor Logic, one of the DTL, RTL and TTL families of Small Scale
Integration (SSI) families of semiconductors made by TI since the
1970's. RTL in regard to HDL, which is Hardware Description Language
is ususally meant to be Register Transfer Level, referring to a level
of abstraction that was first introduced by Gordon Bell in a text
that is used quite a bit in college courses. RTL was first
characterized by ISP, known as Instruction Set Processor, a language
that was used to describe register transfers in computer hardware.
HDL is also used quite a bit to refer to the Verilog language, as
opposed to VHDL, which is the VHISIC Hardware description language.
From sun!rx7.ece.cmu.edu!hage...@nsc.nsc.com Fri Jun 5 13:50:40 1992
Date: Fri, 5 Jun 92 14:55:37 EDT
From: John Hagerman <hage...@rx7.ece.cmu.edu>
To: vas...@berlioz.nsc.com (Vaseem Anjum)
Subject: RTL vs. HDL
Status: RO
Content-Length: 555
X-Lines: 13
RTL: Register Transfer Language, for describing hardware at a level of
abstraction involving control steps, function units, and value
transfers.
HDL: Hardware Description Language, for describing hardware; the level
of abstraction depends on the language. Verilog provides support
for two levels commonly used for simulating hardware: gate level,
and behavior level (of course, this is a simplification).
This definition implies that using "HDL" to mean any particular level
of abstraction will always confuse someone.
- John
From berlioz.nsc.com!voder!apple!sun-barr!cs.utexas.edu!ut-emx!ibmchs!auschs!awdprime.austin.ibm.com!garton.austin.ibm.com!brad Tue Jun 16 09:18:28 PDT 1992
Article: 112 of comp.lang.verilog
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From: br...@garton.austin.ibm.com (Brad Garton)
Newsgroups: comp.lang.verilog
Subject: Re: RTL vs. HDL
Message-ID: <1992Jun15.1...@awdprime.austin.ibm.com>
Date: 15 Jun 92 16:01:44 GMT
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Cindy Eisner writes:
Brad
From berlioz.nsc.com!voder!apple!sun-barr!decwrl!sdd.hp.com!wupost!uunet!Cadence.COM!cadence.com!bammi Mon Jun 15 09:37:57 PDT 1992
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From: ba...@acae127.cadence.com (Jwahar R. Bammi)
Newsgroups: comp.lang.vhdl,comp.lang.verilog
Subject: Re: RTL vs. HDL
Message-ID: <BAMMI.92J...@acae127.cadence.com>
Date: 27 May 92 03:35:57 GMT
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In article <1992Jun5.1...@berlioz.nsc.com> vas...@berlioz.nsc.com (Vaseem Anjum) writes:
>
> Can someone tell me the exact difference between RTL and HDL.
> I've heard different interpretations. I'd like to hear your view.
>
in my view, RTL is just another level of abstraction that your
HDL may or may not support. the way i view it, RTL is a convenient
abstraction of of the actual physical hardware, in which you model and
sequence the actual physical transfers that are possible in the
actual physical design in order to implement desired behaviors. these
transfers may or may not contain delays. from a modelling/simulation
point of view the key feature needed to support the RTL level of
abstraction is that all the transfers possible in a particular control
step occur simultaneously, ie: if you write
a <= b;
b <= a;
the values of `a' and `b' get exchanged. post 1.6 versions (and i
suspect OVI Verilog-HDL) of Verilog-HDL/Verilog-XL have support
RTL modeling that should be sufficient for most intents and purposes.
(the support for RTL is not as rich as in say N.mPC (or N.2) or other
isps like HDLs that were entirely designed around the RTL level of
abstraction)
cheers,
--
--
bang: uunet!cadence!bammi jwahar r. bammi
domain: ba...@cadence.com
GEnie: J.Bammi
CIS: 71515,155
From berlioz.nsc.com!voder!apple!netcomsv!decwrl!sdd.hp.com!cs.utexas.edu!uunet!imp!ca41!cindy Mon Jun 15 09:40:01 PDT 1992
Article: 100 of comp.lang.verilog
Path: berlioz.nsc.com!voder!apple!netcomsv!decwrl!sdd.hp.com!cs.utexas.edu!uunet!imp!ca41!cindy
From: ci...@zoran.hellnet.org (Cindy Eisner)
Newsgroups: comp.lang.verilog
Subject: Re: RTL vs. HDL
Message-ID: <1...@ca41.zoran.hellnet.org>
Date: 9 Jun 92 11:54:05 GMT
References: <1992Jun5.1...@berlioz.nsc.com>
Sender: ne...@ca41.zoran.hellnet.org
Organization: Zoran Microelectronics LTD. Haifa, Israel.
Lines: 30
Nntp-Posting-Host: ca45
In article <1992Jun5.1...@berlioz.nsc.com>, vas...@berlioz.nsc.com (Vaseem Anjum) writes:
>
> Can someone tell me the exact difference between RTL and HDL.
> I've heard different interpretations. I'd like to hear your view.
>
HDL is just any Hardware Description Language, for instance, VHDL, Verilog, etc. RTL is
Register Transfer Level, and it is one of the levels of abstraction usually supported by
an HDL. other levels of abstraction are behavioral (sometimes called algorithmic) and gate
level.
in RTL, each register in the described hardware is declared and assigned, and a clock-by-
clock equivalence with the hardware can be seen even without explicitly coding delays. a
behavioral description, on the other hand, may not intend to a clock-by-clock equivalence to
the described hardware, and if it does, it may achieve the clock-by-clock equivalence using
delays the length of the clock period, for instance, in order to create a pulse, or by other
means than explicitly describing each register.
however, a lot of people use RTL to mean anything synthesizable, and behavioral to mean
all the rest, even if their behavioral is also technically RTL.
--
Cindy Eisner, Tel: 972-4-551551
CAD group, Fax: 972-4-551550
Zoran Microelectronics LTD, E-mail: ci...@Zoran.HellNet.Org
Advanced Technology Center
Haifa 31204, Israel
From berlioz.nsc.com!voder!apple!bionet!uwm.edu!wupost!think.com!unixland!wellspring!elliot Mon Jun 15 09:41:28 PDT 1992
Article: 104 of comp.lang.verilog
Path: berlioz.nsc.com!voder!apple!bionet!uwm.edu!wupost!think.com!unixland!wellspring!elliot
From: ell...@Wellspring.COM (Elliot H. Mednick)
Newsgroups: comp.lang.verilog
Subject: RTL vs. HDL
Message-ID: <708197...@Wellspring.COM>
Date: 10 Jun 92 17:37:21 GMT
References: <1...@ca41.zoran.hellnet.org>
Reply-To: ell...@Wellspring.com
Organization: Wellspring Solutions
Lines: 29
In article <1...@ca41.zoran.hellnet.org> ci...@zoran.hellnet.org writes:
> In article <1992Jun5.1...@berlioz.nsc.com>, vas...@berlioz.nsc.com> (Vaseem Anjum) writes:
> >
> > Can someone tell me the exact difference between RTL and HDL.
> > I've heard different interpretations. I'd like to hear your view.
>
> HDL is just any Hardware Description Language, for instance, VHDL, Verilog,> etc. RTL is
> Register Transfer Level, and it is one of the levels of abstraction usually> supported by
> an HDL. other levels of abstraction are behavioral (sometimes called> algorithmic) and gate
> level.
I think you misunderstood the question (not that it was phrased correctly).
In this case, RTL stands for Register Transfer Language. Before Verilog
and VHDL dominated the industry, there were a slew of so-called hardware
description languages, none of which were widely used and most were specific
to a certain level of abstraction. The subset of these which modeled
hardware at what we now call the register-transfer level were called
Register Transfer Languges. There was one RTL that almost became
a widely-used standard, but I forget its name (something like OCCAM(?)).
There were several papers presented in the mid 1970's on hardware description
languages and register transfer languages. If you are interested in the
references (for a historical perspective, perhaps?), it would not be too
difficult for me to dig them up.
--
Elliot H. Mednick P.O. Box 150
Wellspring Solutions Sutton, MA. 01590
ell...@Wellspring.com +1 508 865 7271
From berlioz.nsc.com!voder!apple!usc!zaphod.mps.ohio-state.edu!moe.ksu.ksu.edu!ux1.cso.uiuc.edu!m.cs.uiuc.edu!swine.cs.uiuc.edu!hughes Mon Jun 15 09:42:37 PDT 1992
Article: 106 of comp.lang.verilog
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From: hug...@swine.cs.uiuc.edu (Eric Hughes)
Newsgroups: comp.lang.verilog
Subject: Re: RTL vs. HDL
Message-ID: <1992Jun11.1...@m.cs.uiuc.edu>
Date: 11 Jun 92 13:44:19 GMT
References: <1...@ca41.zoran.hellnet.org> <708197...@Wellspring.COM>
Sender: ne...@m.cs.uiuc.edu (News Database (admin-Mike Schwager))
Organization: University of Illinois, Dept. of Comp. Sci., Urbana, IL
Lines: 24
Dave Rich; x6337
|>
|> What do I want from you? How about telling me which HDL is most popular
|> in industry today (doesn't matter which one I get started with because
|> the company has their own proprietary HDL anyway)? What public domain
|> HDL is available and where can I get a copy of the software? I think
|> there's a PD VHDL somewhere, but you'll have to feed me more info on
|> that one. How about suggesting some good books, tutorial type hopefully,
|> that I can go buy? Any other suggestions?????
|>
--
My advice about learning an HDL if you already have a strong software
background: don't worry about it! My experience teaching Verilog shows
me that anyone with C or Pascal knowledge and digital design can pick up
Verilog in less than 2 days. VHDL in less than a week. Many univiersties
have a copy of Verilog or VHDL being used in at least one project.
Check with the Graduate department to see if you can get spend a few
hours with it. (or at least read the manuals)
____________________________________________________________
Dave Rich tele 1-508-934-0337 email dav...@cadence.com
Cadence Design, 2 Lowell Research Ctr., Lowell MA 01852-4995
____________________________________________________________