SystemVerilog Constants?

[Amal]

Is this not valid in SystemVerilog?

6: const int W = 5;
7: const bit [W-1:0] x = 'b0;

I get the following error in Modelsim

** Error: test.sv(7): Range must be bounded by constant expressions.

This same syntax seems to be accepted as part of a module parameters!

module constant #(
parameter int W = 5;
parameter bit [W-1:0] x = 'b0;
)

Any ideas?
-- Amal

[Jonathan Bromley]

A "const" variable in SV is simply a variable that can be written
only once, on initialization. That's not the same as a parameter.
Parameters are fixed at _elaboration_ time. I'll double-check with
the LRM, but I'm fairly sure that Modelsim is correct here.

So, as you can easily see, "const" doesn't mean "constant" :-)
There are a few other Humpty Dumpty [*] keywords in SV; "virtual"
is my favourite (three meanings, at the last count). I suppose
you can justify it on the grounds that it limits the population
explosion of keywords.

[*] Check out Humpty Dumpty's conversation with Alice about
the meaning of words.
--
Jonathan Bromley, Consultant

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[Jason Zheng]

On Mon, 8 Dec 2008 10:50:14 -0800 (PST)

Amal <akhai...@gmail.com> wrote:

> 6: const int W = 5;
> 7: const bit [W-1:0] x = 'b0;
>
> I get the following error in Modelsim
>
> ** Error: test.sv(7): Range must be bounded by constant expressions.
>
> This same syntax seems to be accepted as part of a module parameters!
>
> module constant #(
> parameter int W = 5;
> parameter bit [W-1:0] x = 'b0;
> )

Not an SV expert, but I remember that const values can be set during
simulation, whereas parameters are set during elaboration. In your
first case, the compiler does not know how much space to reserve for x,
since const int w will not be evaluated until simulation time.

In the second case, W is specified as a parameter type, so this allows
W to be used to specify the size of another parameter x.

The fundamental difference between a const int and a parameter int is
that a const int is still a variable from the compiler's point of view,
where as a parameter is a true constant that can be used to define
range or dimensions.

hth,

Jason Zheng

--
Humorists always sit at the children's table.
-- Woody Allen

[Amal]

Yes I think I confused that one. I should have used localparam
instead.

Thanks,
-- Amal

On Dec 8, 2:18 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
> On Mon, 8 Dec 2008 10:50:14 -0800 (PST)
>

[Amal]

Is localparam used for constant array declarations inside packages as
well? How would you declare a constant table (multi-dimensional
array) in SV inside a package?

Sorry for dumb questions, I have a good VHDL background and I am
trying to switch to SV for design and it confuses me when I try to
find a matching constuct in SV.

-- Amal