comp.lang.verilog

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林帥哥, xinlnix g3

Aug 8

How to implant the artificial neural network model to Verilog-A for circuit simulation

xinlnix g 在 2023年3月14日星期二晚上10:45:18 [UTC+8] 的信中寫道： > 在 2022年9月29日星期四 UTC+8 11:19:22，<林帥哥> 写

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How to implant the artificial neural network model to Verilog-A for circuit simulation

xinlnix g 在 2023年3月14日星期二晚上10:45:18 [UTC+8] 的信中寫道： > 在 2022年9月29日星期四 UTC+8 11:19:22，<林帥哥> 写

Aug 8

Shivangi Sharma

Jun 29

Hi all, how to connect different two testbench scoreboard in common testbench scoreboard in system

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Hi all, how to connect different two testbench scoreboard in common testbench scoreboard in system

Jun 29

Chloe, … gnuarm.del...@gmail.com8

Jun 24

Use of Both Posedge Clk and Negedge Clock

On Friday, June 23, 2023 at 10:19:59 PM UTC-4, e liu wrote: > ppo...@gmail.com 在 2005年5月27日星期五下午5

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Use of Both Posedge Clk and Negedge Clock

On Friday, June 23, 2023 at 10:19:59 PM UTC-4, e liu wrote: > ppo...@gmail.com 在 2005年5月27日星期五下午5

Jun 24

Qazi Zabeer, Charlie2

Jun 5

How can I stop the simualtion at stop bit for i2c master verilog code?

On 6/5/2023 6:15 PM, Qazi Zabeer wrote: > > I am trying to write Verilog code for I2C master

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How can I stop the simualtion at stop bit for i2c master verilog code?

On 6/5/2023 6:15 PM, Qazi Zabeer wrote: > > I am trying to write Verilog code for I2C master

Jun 5

Apr 20

FPGA + ASIC PQC Security IP / hardware root of trust by Xiphera

Are you tired of worrying about the security of your FPGA/ASIC system? Allow me to introduce Xiphera

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FPGA + ASIC PQC Security IP / hardware root of trust by Xiphera

Are you tired of worrying about the security of your FPGA/ASIC system? Allow me to introduce Xiphera

Apr 20

VMSK, … Charlie9

Apr 4

Need to understand a mux implementation in verilog code

On Sunday, April 2, 2023 at 1:17:54 AM UTC+5:30, Charlie wrote: > On 4/1/2023 2:47 PM, gnuarm.del.

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Need to understand a mux implementation in verilog code

On Sunday, April 2, 2023 at 1:17:54 AM UTC+5:30, Charlie wrote: > On 4/1/2023 2:47 PM, gnuarm.del.

Apr 4

Mar 10

matrix multiplier is not working

I am trying to design a matrix multiplier in Verilog using systolic array architecture. If I test the

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matrix multiplier is not working

I am trying to design a matrix multiplier in Verilog using systolic array architecture. If I test the

Mar 10

Feb 28

Help in Verilog Code & Testbench

I am writing verilog code & testbench to convert from octal number to binary number but I am not

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Help in Verilog Code & Testbench

I am writing verilog code & testbench to convert from octal number to binary number but I am not

Feb 28

S C Creaser, … farnood mb3

Jan 13

Help with `timescale compiler directive please!

On Wednesday, July 21, 1993 at 8:59:47 AM UTC-7, Avrum Warshawsky wrote: > SC Creaser (scc...@ecs.

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Help with `timescale compiler directive please!

On Wednesday, July 21, 1993 at 8:59:47 AM UTC-7, Avrum Warshawsky wrote: > SC Creaser (scc...@ecs.

Jan 13

mag, … Gurmeet Arora5

12/15/22

Re: Verilog Implementation of a Feed Forward Neural Network

On Wednesday, September 28, 2022 at 8:20:55 PM UTC-7, chuanj...@gmail.com wrote: > do you have

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Re: Verilog Implementation of a Feed Forward Neural Network

On Wednesday, September 28, 2022 at 8:20:55 PM UTC-7, chuanj...@gmail.com wrote: > do you have

12/15/22

12/14/22

Excess 3 Adder: Add 2 three digits numbers in excess 3.

Excess 3 Adder: Add 2 three digits numbers in excess 3. ex. 998+345 in excess 3. i don't have any

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Excess 3 Adder: Add 2 three digits numbers in excess 3.

Excess 3 Adder: Add 2 three digits numbers in excess 3. ex. 998+345 in excess 3. i don't have any

12/14/22

light, … Murat Can Işık3

12/7/22

sixteen bits adder

Make it ready and send it back, it doesn't seem to be a question. Stackoverflow would be

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sixteen bits adder

Make it ready and send it back, it doesn't seem to be a question. Stackoverflow would be

12/7/22

Javed Akhter Mondal, Muzaffer Kal2

12/3/22

Modelling duffing oscillator in Verilog

On Friday, November 25, 2022 at 4:42:01 AM UTC-8, akhte...@gmail.com wrote: > Can anyone help me

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Modelling duffing oscillator in Verilog

On Friday, November 25, 2022 at 4:42:01 AM UTC-8, akhte...@gmail.com wrote: > Can anyone help me

12/3/22

10/6/22

VPI passing argument

Hi , I want to check for a signal inside a subsystem. I know the top level module name. and i want to

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VPI passing argument

Hi , I want to check for a signal inside a subsystem. I know the top level module name. and i want to

10/6/22

9/26/22

Research Assistantship at the Graduate School, Dept. of Computer Engineering, Hallym University, Korea

Research Assistantship at the Graduate School, Dept. of Computer Engineering, Hallym University,

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Research Assistantship at the Graduate School, Dept. of Computer Engineering, Hallym University, Korea

Research Assistantship at the Graduate School, Dept. of Computer Engineering, Hallym University,

9/26/22

9/14/22

No transition in the state

Hi I am writing SPI master for an ADC communication. I wrote the verilog code as shown but when I

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No transition in the state

Hi I am writing SPI master for an ADC communication. I wrote the verilog code as shown but when I

9/14/22

Varun Jindal, … mostafa hosseini9

8/3/22

Tool to flatten a verilog design.

On Tuesday, September 14, 2004 at 1:47:02 PM UTC+4:30, Varun Jindal wrote: > hello, > i am

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Tool to flatten a verilog design.

On Tuesday, September 14, 2004 at 1:47:02 PM UTC+4:30, Varun Jindal wrote: > hello, > i am

8/3/22

alb, Raveen Kumar2

7/29/22

vim and ctags/cscope for (System}Verilog

On Thursday, 1 December, 2016 at 4:00:26 am UTC+5:30, alb wrote: > Hi there, > > does anyone

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vim and ctags/cscope for (System}Verilog

On Thursday, 1 December, 2016 at 4:00:26 am UTC+5:30, alb wrote: > Hi there, > > does anyone

7/29/22

6/23/22

Read large MNIST file in System Verilog

Hi all, I am trying to read the first 200 rows in MNIST file which contains grayscale data 0-255 in

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Read large MNIST file in System Verilog

Hi all, I am trying to read the first 200 rows in MNIST file which contains grayscale data 0-255 in

6/23/22

okhajut, Kevin2

6/2/22

Pitfall with mixing of blocking and non-blocking assignments in SystemVerilog

okhajut schrieb am Sonntag, 20. Februar 2022 um 15:05:24 UTC-7: > VHDL has a clear distinction

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Pitfall with mixing of blocking and non-blocking assignments in SystemVerilog

okhajut schrieb am Sonntag, 20. Februar 2022 um 15:05:24 UTC-7: > VHDL has a clear distinction

6/2/22

okhajut, Kevin2

6/2/22

By design, why does SystemVerilog logic type has 4-states possible but VHDL std_logic type has 9-states possible?

okhajut schrieb am Sonntag, 20. Februar 2022 um 14:49:19 UTC-7: > The SystemVerilog logic type can

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By design, why does SystemVerilog logic type has 4-states possible but VHDL std_logic type has 9-states possible?

okhajut schrieb am Sonntag, 20. Februar 2022 um 14:49:19 UTC-7: > The SystemVerilog logic type can

6/2/22

Tom Szolyga, … Kevin5

6/2/22

Bit Numbering in Verilog

> wire[31: 0] vA; // OK > wire[ 0: 7] vX; //OK > assign vx = vA[0:7]; //this one will yield

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Bit Numbering in Verilog

> wire[31: 0] vA; // OK > wire[ 0: 7] vX; //OK > assign vx = vA[0:7]; //this one will yield

6/2/22

GAYATHRI U, Gabor2

5/29/22

Issue with file operations in verilog

On Friday, 5/27/2022 7:56 AM, GAYATHRI U wrote: > module(input clk); > integer fd; > initial

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Issue with file operations in verilog

On Friday, 5/27/2022 7:56 AM, GAYATHRI U wrote: > module(input clk); > integer fd; > initial

5/29/22

KRISHNA CHAITHANYA, Hariprasad Bhat2

5/1/22

Verilog Code for Parallel CRC encoding and Decoding using LFSR

On Friday, April 22, 2022 at 4:17:59 PM UTC+5:30, chait...@gmail.com wrote: > Kindly suggest or

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Verilog Code for Parallel CRC encoding and Decoding using LFSR

On Friday, April 22, 2022 at 4:17:59 PM UTC+5:30, chait...@gmail.com wrote: > Kindly suggest or

5/1/22

SweetMusic, … Beniamin Antal-Vaida6

3/28/22

Up/Down Binary Counter with Dynamic Count-to Flag

Pe miercuri, 25 martie 2020, la 22:00:39 UTC+2, robee...@gmail.com a scris: > joi, 15 mai 2008, 14

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Up/Down Binary Counter with Dynamic Count-to Flag

Pe miercuri, 25 martie 2020, la 22:00:39 UTC+2, robee...@gmail.com a scris: > joi, 15 mai 2008, 14

3/28/22

okhajut, … Anssi Saari5

3/22/22

Accessing DUT internal signals in a SystemVerilog testbench

Gabor <nos...@nospam.com> writes: > No. It's been part of Verilog for a long time. In

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Accessing DUT internal signals in a SystemVerilog testbench

Gabor <nos...@nospam.com> writes: > No. It's been part of Verilog for a long time. In

3/22/22

Tom Szolyga, … okhajut4

2/20/22

Verilog for Cyclone IV

On Sunday, 5 September 2021 at 18:54:17 UTC+1, tszo...@pacbell.net wrote: > I am trying to program

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Verilog for Cyclone IV

On Sunday, 5 September 2021 at 18:54:17 UTC+1, tszo...@pacbell.net wrote: > I am trying to program

2/20/22

Tanishk Singh, Richard Damon2

11/7/21

Verilog HDL Finite State Machine - Detecting decimal number

On 11/7/21 12:56 AM, Tanishk Singh wrote: > Hi all, > > I am trying to build a sequence

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Verilog HDL Finite State Machine - Detecting decimal number

On 11/7/21 12:56 AM, Tanishk Singh wrote: > Hi all, > > I am trying to build a sequence

11/7/21

9/28/21

VPI: How to walk hierarchy that contains generate blocks

How does one use VPI walk the hierarchy of a design that contains generate blocks? I have found that

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VPI: How to walk hierarchy that contains generate blocks

How does one use VPI walk the hierarchy of a design that contains generate blocks? I have found that

9/28/21

Niharika Behera, … Richard Damon10

9/16/21

On 9/16/21 11:08 AM, TJ Edmister wrote: > On Sun, 05 Sep 2021 01:25:16 -0400, Niharika Behera >

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On 9/16/21 11:08 AM, TJ Edmister wrote: > On Sun, 05 Sep 2021 01:25:16 -0400, Niharika Behera >

9/16/21

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