On Tuesday, 14 September 2021 at 15:07:40 UTC+1, Wayne morellini wrote:
> On Tuesday, 14 September 2021 at 6:43:38 pm UTC+10, jpit...@gmail.com
> > On Tuesday, 14 September 2021 at 08:38:02 UTC+1, Wayne morellini wrote:
> > I thought I have a quick look and went to Europractice to see how much it costs to have my own chip
> > - assuming a design is done and ready for manufacturing:
> > https://europractice-ic.com/wp-content/uploads/2021/01/Pricelist-EUROPRACTICE-Miniasic_5.pdf
> > Multiproject Wafer at 130 nm, 25 samples about 6 000 dollars.
> > Where is the problem ?
> We want a much newer better process. It's cheap like GA used to pay. To get the final design bug free and higher performance might require 50 runs or more.
> From past forthday, I understand GA was loosing cheap access to the 180nm,
so were on the look out for something better and cheaper.
When manufacturing, you need cheap volume capacity
to compete and offer customers parts from.
GA144 has been with us as is now for more that 10 years,
and the way it was designed is interesting, and unique
but I would not like to buy a chip that only Chuck can modify with his own tools if required.
Standard tools proven with the foundry are a better choice I think.
> On Tuesday, September 14, 2021 at 6:51:39 PM UTC+10, jpit...@gmail.com
> > On Tuesday, 14 September 2021 at 09:43:38 UTC+1, Jurgen Pitaske wrote:
> > > On Tuesday, 14 September 2021 at 08:38:02 UTC+1, Wayne morellini wrote:
> > Or to make it closer to a decision:
> > Which Forth chip desigs are available at opencores or elsewhere in VHDL to make a chip?
> > We could always do a first run based on Bernd Paysan's B16 I assume if he agrees ?
> Dr Ting had a range of designs, Ike 32 bit and 64 bit, for FPGA, but I think they might have VHDL designs.
> On Tuesday, 14 September 2021 at 7:46:59 pm UTC+10, jpit...@gmail.com
> > On Tuesday, 14 September 2021 at 09:51:39 UTC+1, Jurgen Pitaske wrote:
> > > On Tuesday, 14 September 2021 at 09:43:38 UTC+1, Jurgen Pitaske wrote:
> > > > On Tuesday, 14 September 2021 at 08:38:02 UTC+1, Wayne morellini wrote:
> > As I have just been told,
> > a requirement would be to have a testbench
> > and test bench results as well to move forward.
> Yes. It's a time process. A design doesn't just go straight into a new fab process optimised, but requires optimisation runs.
Please do not tell granny how to suck eggs.
I have been in VHDL and ASICs for the last 25 years.
Not designing myself - but making sure they come to a success.
> On Tuesday, 14 September 2021 at 9:14:45 pm UTC+10, jpit...@gmail.com
> > On Tuesday, 14 September 2021 at 10:52:31 UTC+1, minf...@arcor.de
> > > jpit...@gmail.com
schrieb am Dienstag, 14. September 2021 um 11:46:59 UTC+2:
> > > You need results because you can't compete pricewise
> > > https://cpldcpu.wordpress.com/2019/08/12/the-terrible-3-cent-mcu/
> > For the moment price does not matter. And who would use 1 million anyway?
> Pretty much any real success to pay for things, requires volume.
> > I heard a comment like - put it into an FPGA.
> > We have done this with the 1802 and FIG Forth for the book project in Lattice FPGA.
> > and somewhere it is stated, that this FPGA version is roughly 200x faster than the original.
> Which is what to expect with FPGA, at a higher cost, more energy and size.
> Are you the one that was trying to do a web book tablet with the shboom decades ago?
I just came back to Forth about 15 years ago
and would not touch such a complex project.
The issue here would be how to sell it against the rest of the ones available
- where would the advantage be?
For exapmle I have not seen even existing tablets modified into Forth machines with a similar functionality - this would be easier.
> > But implemented in a suitable ASIC technology should give another factior of 2 - 10
> > see here
> > https://www.amazon.co.uk/gp/product/B01N42VLJE/ref=dbs_a_def_rwt_bibl_vppi_i0
> > and here
> > https://wiki.forth-ev.de/doku.php/projects:fig-forth-1802-fpga:start
> > So, this is a background project for me now to find out.
> > For now it is the cost of a few emails and phone calls,
> > and we will see when the need for money comes up to take it further.
> I frankly might care that a newer better design is used,
but I also don't care if people do something else better than misc, it is progress.
Ting's 32 bit and 64 bit designs are probably more substantial designs to use than the b16.
But, people can put multiple designs on a shuttle run together, to save costs.
> But the MQCA technology is able to run at close to the maximum physical efficiency possible,
some million times less energy than some past desktop processor.
Even if you only get 1000 better efficiency, you get a lot of processing density
in very confined spaces on little energy, even parasitic, for IOT,
in something you can possibly manufacture and control production of, at a good price.
It is a natural alternative to FPGAs. GA would be better to look into that.
EP32 is part of my Forth Bookshelf, so I know it
At the moment I try to find out about the costs and have a route from VHDL to silicon.
Which design is then used is a separate decision.
Based on costs and availibility
There might be many options people here can suggest.
And Berd's design I know a little bit about.
I have asked him if it could be used as one option.
One name option I have chosen already: AIR FORTH 1 - An Intelligent RISC FORTH chip number 1