Chuck;'s Birthday

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Jurgen Pitaske

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Sep 9, 2021, 7:59:50 AMSep 9
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It is Chuck Moore's 83rd birthday today.
You might want to send some greetings,
here a link to his facebook - or you might have his email address .https://www.facebook.com/charleshavicemoore

Paul Rubin

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Sep 9, 2021, 1:37:31 PMSep 9
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Happy 83rd birthday Chuck! Or perhaps I should say:

83 birthday Chuck happy

dxforth

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Sep 9, 2021, 11:32:45 PMSep 9
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No birthday required

begin grokforth until happy

Wayne morellini

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Sep 14, 2021, 3:37:11 AMSep 14
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Happy Birthday Chuck.

Been a long time. Turns out I have had a terminal disease.

Anyway. What's the future of forth chips.

I'm not much interested in forth, but the post forth chips. The future is forth like chips.

Misc is only the first entry. Where do we go from here? Forth byte sized VM, covered in another thread, is a handy indicator of a general alternative direction for small chips. But there is apparently a 6Ghz chip coming in another thread. I have also been trying to track down cheap alternative fab space, but apparently the Europeans will modern fab a chip, and Google will pay for fab of open source efforts, if I'm reading it right. This brings some ideas in mind. While I'm interested in commercial efforts, to really push paid development, I am with Musk in tossing the free competitive market a bone, to encourage it.

The byte sized forth is handy, in that the bytes can refer to either the top bits of an address space, or vector locations. That's very simple. That's enough for simple embedded use. 16-bits would give enough for more complex programs. Going a step further, each program space could get its own
16 bits of top addressing, and further, a dynamic seperate 16 bits of data space. The next version, the data space can be attached to each call. You then go to transfer/shared space attached. Local jump addressing gets local space. My old design proposals looked into these things. Currently, I am wanting to start on a new type of processing chip, with stack based elements to it, far better than forth. Now, I had also issues with the above sort of structures at first, because a simple top 8 bits of an 16 bit address space means 256 byte boundaries, and left over space (which could be used for data, but then you would have to switch if using a seperate address space) and if over 256 bytes, you loose at least one call slot on direct addressing, and vector needs on chip associative memory to avoid a big hit on the calls. Anyway, it's still very simple. It's a way that 18 bit misc can work also, and that's very sufficient call numbers and address space. Now, each program gets its own 256 calls potential, or 16 bits worth.

Saving memory, is no longer such an issue, packing words for higher speed, is no longer such an issue. As, there is more than enough memory often, and a severe limit on speed, not needed for much embedded.

So, these schemes are good.

The 8 bit call system could be added to existing 8 bit processors, as an extra instruction, or instruction mode to develop to, transfering development over too. Such modes can have a complete misc instruction set plugged into the chips architecture, and a few individual instructions can make up for deficiencies in normal mode chips. It can also be sold as it's own chip, to develop for. The 16 bit modes also being able to be used on Arm or Risc-V open source processor. The more complex dynamic address space gives reasonable sized systems capability under an os. Now, a more conventional 32 bit+ circuit can also be done. By incorporating on RISC-V or Arm, it's possible in as little as 1000 transistors to have a forth stack orientated environment under an Linux operating system. The Linux operating system assigning each stack environment space it's own area, allowing for sand boxing. This is a slow inclusion of the environment into other eco systems, but allowing general system functions to be handled by Linux or Android, or other systems. The advantage is simplicity, and options for 1000 transistor plus control chips able to be used in many places in embedded. With forth like languages coding. For internet of things, 1000 transistors plus cores, even in special processes capable of over 6Ghz, is very useful. I'm not talking silicon here, there are many processes that don't make bulk low cost consumer sales sense, which may, or may not, be useful, but a spec of a chip able to go low energy or speed up to high speed, is desirable in certain applications.

Now. An honorary mention to Rick. Who years back, wanted to use misc for a software radio. In modern high speed wireless terms, the idea wasn't wrong, just wrong target platform. Misc wasn't going do much past low speed and embedded standards
However, the above in an array, with some cores having large work spaces, and some, or all, a shared work space bus technique, for passing or direct writing, is useful for more demanding modern wireless standards, able to overclock to high speeds. It is also somebody like AT&T or Cisco, might like to invest in the development of. Arm Thumb 2 is not the final answer.

Wayne morellini

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Sep 14, 2021, 3:38:02 AMSep 14
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On the subject of fabbing. We have high school kids online making their own fabs at home. But, it is a bit extreme. We have that French and Google stuff. But, unless you want to give your Intellectual property away, it's a bit useless. However, misc chips have worked in the 500mhz range, that magnetic quantum cellular automata can work in. It's possible to 3D print, or even print MQCA circuites, even to use normal magnets to emulate the effect. Theoretically, you could make a forth chip, by hand. Something I wanted to do before I got too sick. It's also in the range of simplicity which Chuck likes. It might not go 5ghz+ yet, but a lot of things don't need to go more than 500mhz. You are also getting to a point of simplicity, where pressed circuit making is attractive. This is where physical circuit layers are pressed or rolled onto a chip, to make it.

A lesser mention, goes to gate arrays finalised with a printed top layer.

Frankly, I would like to kick start a massive fine pitch 3D printing system. Desktop foundry, if trying to print the right technology. The price, maybe $1000. It's a bit of a sophisticated twist. 10-2 micron is enough for 3D printing, but how small can it be pushed. The right technique can make smaller particles.

Jurgen Pitaske

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Sep 14, 2021, 4:43:38 AMSep 14
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I thought I have a quick look and went to Europractice to see how much it costs to have my own chip
- assuming a design is done and ready for manufacturing:

https://europractice-ic.com/wp-content/uploads/2021/01/Pricelist-EUROPRACTICE-Miniasic_5.pdf
Multiproject Wafer at 130 nm, 25 samples about 6 000 dollars.
Where is the problem ?
Or more importantly is anybody interested, why did it not happen until now?
200 $ each for 25 parties and you get your very special FORTH CHIP.
And move it to production later if there is the interest of the market..

I think, the GA144 chip was 180 nm at MOSIS 10 or 12 years ago.
And the new version GA144A2x seems to have no date of birth yet,
and no feature size compared to the 180nm of the existing version mentioned, see from their website:

Latest developments:
As of Spring 2021, shipments of the EVB002 evaluation kit and of G144A12 chips continue to be made. The arrayForth 3 integrated development system is in use with no reported problems.
Design of a new chip, G144A2x, continues; this will be upward compatible with the G144A12, with significant improvements. Development of Application Notes, including that of a solftware defined GPS receiver, continues.

Jurgen Pitaske

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Sep 14, 2021, 4:51:39 AMSep 14
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Or to make it closer to a decision:
Which Forth chip desigs are available at opencores or elsewhere in VHDL to make a chip?

We could always do a first run based on Bernd Paysan's B16 I assume if he agrees ?

Jurgen Pitaske

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Sep 14, 2021, 5:46:59 AMSep 14
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As I have just been told,
a requirement would be to have a testbench
and test bench results as well to move forward.

minf...@arcor.de

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Sep 14, 2021, 5:52:31 AMSep 14
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jpit...@gmail.com schrieb am Dienstag, 14. September 2021 um 11:46:59 UTC+2:
> As I have just been told,
> a requirement would be to have a testbench
> and test bench results as well to move forward.

You need results because you can't compete pricewise
https://cpldcpu.wordpress.com/2019/08/12/the-terrible-3-cent-mcu/

Jurgen Pitaske

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Sep 14, 2021, 7:14:45 AMSep 14
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For the moment price does not matter. And who would use 1 million anyway?
I want to find out how to get from VHDL to silicon, after having been in this 20 years ago
and what a min price is to get 20 to 100 dies.
and a b16 core would be an option if Bernd agrees.
Only then one could really judge.
Simulation is fine,
and
I heard a comment like - put it into an FPGA.
We have done this with the 1802 and FIG Forth for the book project in Lattice FPGA.
and somewhere it is stated, that this FPGA version is roughly 200x faster than the original.
But implemented in a suitable ASIC technology should give another factior of 2 - 10
see here
https://www.amazon.co.uk/gp/product/B01N42VLJE/ref=dbs_a_def_rwt_bibl_vppi_i0

and here
https://wiki.forth-ev.de/doku.php/projects:fig-forth-1802-fpga:start

So, this is a background project for me now to find out.
For now it is the cost of a few emails and phone calls,
and we will see when the need for money comes up to take it further.

Wayne morellini

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Sep 14, 2021, 10:07:40 AMSep 14
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On Tuesday, 14 September 2021 at 6:43:38 pm UTC+10, jpit...@gmail.com wrote:
> On Tuesday, 14 September 2021 at 08:38:02 UTC+1, Wayne morellini wrote:

> I thought I have a quick look and went to Europractice to see how much it costs to have my own chip
> - assuming a design is done and ready for manufacturing:
>
> https://europractice-ic.com/wp-content/uploads/2021/01/Pricelist-EUROPRACTICE-Miniasic_5.pdf
> Multiproject Wafer at 130 nm, 25 samples about 6 000 dollars.
> Where is the problem ?

We want a much newer better process. It's cheap like GA used to pay. To get the final design bug free and higher performance might require 50 runs or more.

From past forthday, I understand GA was loosing cheap access to the 180nm, so were on the look out for something better and cheaper. When manufacturing, you need cheap volume capacity to compete and offer customers parts from.
Dr Ting had a range of designs, Ike 32 bit and 64 bit, for FPGA, but I think they might have VHDL designs.


On Tuesday, 14 September 2021 at 7:46:59 pm UTC+10, jpit...@gmail.com wrote:
> On Tuesday, 14 September 2021 at 09:51:39 UTC+1, Jurgen Pitaske wrote:
> > On Tuesday, 14 September 2021 at 09:43:38 UTC+1, Jurgen Pitaske wrote:
> > > On Tuesday, 14 September 2021 at 08:38:02 UTC+1, Wayne morellini wrote:

> As I have just been told,
> a requirement would be to have a testbench
> and test bench results as well to move forward.

Yes. It's a time process. A design doesn't just go straight into a new fab process optimised, but requires optimisation runs.


On Tuesday, 14 September 2021 at 9:14:45 pm UTC+10, jpit...@gmail.com wrote:
> On Tuesday, 14 September 2021 at 10:52:31 UTC+1, minf...@arcor.de wrote:
> > jpit...@gmail.com schrieb am Dienstag, 14. September 2021 um 11:46:59 UTC+2:
..
> > You need results because you can't compete pricewise
> > https://cpldcpu.wordpress.com/2019/08/12/the-terrible-3-cent-mcu/
> For the moment price does not matter. And who would use 1 million anyway?

Pretty much any real success to pay for things, requires volume.
..

> I heard a comment like - put it into an FPGA.
> We have done this with the 1802 and FIG Forth for the book project in Lattice FPGA.
> and somewhere it is stated, that this FPGA version is roughly 200x faster than the original.

Which is what to expect with FPGA, at a higher cost, more energy and size.

Are you the one that was trying to do a web book tablet with the shboom decades ago?

> But implemented in a suitable ASIC technology should give another factior of 2 - 10
> see here
> https://www.amazon.co.uk/gp/product/B01N42VLJE/ref=dbs_a_def_rwt_bibl_vppi_i0
>
> and here
> https://wiki.forth-ev.de/doku.php/projects:fig-forth-1802-fpga:start
>
> So, this is a background project for me now to find out.
> For now it is the cost of a few emails and phone calls,
> and we will see when the need for money comes up to take it further.


I frankly might care that a newer better design is used, but I also don't care if people do something else better than misc, it is progress. Ting's 32 bit and 64 bit designs are probably more substantial designs to use than the b16. But, people can put multiple designs on a shuttle run together, to save costs.

But the MQCA technology is able to run at close to the maximum physical efficiency possible, some million times less energy than some past desktop processor. Even if you only get 1000 better efficiency, you get a lot of processing density in very confined spaces on little energy, even parasitic, for IOT, in something you can possibly manufacture and control production of, at a good price. It is a natural alternative to FPGAs. GA would be better to look into that.

Jurgen Pitaske

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Sep 14, 2021, 11:55:20 AMSep 14
to
On Tuesday, 14 September 2021 at 15:07:40 UTC+1, Wayne morellini wrote:
> On Tuesday, 14 September 2021 at 6:43:38 pm UTC+10, jpit...@gmail.com wrote:
> > On Tuesday, 14 September 2021 at 08:38:02 UTC+1, Wayne morellini wrote:
>
> > I thought I have a quick look and went to Europractice to see how much it costs to have my own chip
> > - assuming a design is done and ready for manufacturing:
> >
> > https://europractice-ic.com/wp-content/uploads/2021/01/Pricelist-EUROPRACTICE-Miniasic_5.pdf
> > Multiproject Wafer at 130 nm, 25 samples about 6 000 dollars.
> > Where is the problem ?
> We want a much newer better process. It's cheap like GA used to pay. To get the final design bug free and higher performance might require 50 runs or more.
>
> From past forthday, I understand GA was loosing cheap access to the 180nm,
so were on the look out for something better and cheaper.
When manufacturing, you need cheap volume capacity
to compete and offer customers parts from.

GA144 has been with us as is now for more that 10 years,
and the way it was designed is interesting, and unique
but I would not like to buy a chip that only Chuck can modify with his own tools if required.
Standard tools proven with the foundry are a better choice I think.

> On Tuesday, September 14, 2021 at 6:51:39 PM UTC+10, jpit...@gmail.com wrote:
> > On Tuesday, 14 September 2021 at 09:43:38 UTC+1, Jurgen Pitaske wrote:
> > > On Tuesday, 14 September 2021 at 08:38:02 UTC+1, Wayne morellini wrote:
>
> > Or to make it closer to a decision:
> > Which Forth chip desigs are available at opencores or elsewhere in VHDL to make a chip?
> >
> > We could always do a first run based on Bernd Paysan's B16 I assume if he agrees ?

> Dr Ting had a range of designs, Ike 32 bit and 64 bit, for FPGA, but I think they might have VHDL designs.

> On Tuesday, 14 September 2021 at 7:46:59 pm UTC+10, jpit...@gmail.com wrote:
> > On Tuesday, 14 September 2021 at 09:51:39 UTC+1, Jurgen Pitaske wrote:
> > > On Tuesday, 14 September 2021 at 09:43:38 UTC+1, Jurgen Pitaske wrote:
> > > > On Tuesday, 14 September 2021 at 08:38:02 UTC+1, Wayne morellini wrote:
> > As I have just been told,
> > a requirement would be to have a testbench
> > and test bench results as well to move forward.

> Yes. It's a time process. A design doesn't just go straight into a new fab process optimised, but requires optimisation runs.

Please do not tell granny how to suck eggs.
I have been in VHDL and ASICs for the last 25 years.
Not designing myself - but making sure they come to a success.

> On Tuesday, 14 September 2021 at 9:14:45 pm UTC+10, jpit...@gmail.com wrote:
> > On Tuesday, 14 September 2021 at 10:52:31 UTC+1, minf...@arcor.de wrote:
> > > jpit...@gmail.com schrieb am Dienstag, 14. September 2021 um 11:46:59 UTC+2:
> ..
> > > You need results because you can't compete pricewise
> > > https://cpldcpu.wordpress.com/2019/08/12/the-terrible-3-cent-mcu/
> > For the moment price does not matter. And who would use 1 million anyway?
> Pretty much any real success to pay for things, requires volume.
> ..
> > I heard a comment like - put it into an FPGA.
> > We have done this with the 1802 and FIG Forth for the book project in Lattice FPGA.
> > and somewhere it is stated, that this FPGA version is roughly 200x faster than the original.
> Which is what to expect with FPGA, at a higher cost, more energy and size.
>
> Are you the one that was trying to do a web book tablet with the shboom decades ago?

Definitely not.
I just came back to Forth about 15 years ago
and would not touch such a complex project.
The issue here would be how to sell it against the rest of the ones available
- where would the advantage be?
For exapmle I have not seen even existing tablets modified into Forth machines with a similar functionality - this would be easier.

> > But implemented in a suitable ASIC technology should give another factior of 2 - 10
> > see here
> > https://www.amazon.co.uk/gp/product/B01N42VLJE/ref=dbs_a_def_rwt_bibl_vppi_i0
> >
> > and here
> > https://wiki.forth-ev.de/doku.php/projects:fig-forth-1802-fpga:start
> >
> > So, this is a background project for me now to find out.
> > For now it is the cost of a few emails and phone calls,
> > and we will see when the need for money comes up to take it further.

> I frankly might care that a newer better design is used,
but I also don't care if people do something else better than misc, it is progress.
Ting's 32 bit and 64 bit designs are probably more substantial designs to use than the b16.
But, people can put multiple designs on a shuttle run together, to save costs.
>
> But the MQCA technology is able to run at close to the maximum physical efficiency possible,
some million times less energy than some past desktop processor.
Even if you only get 1000 better efficiency, you get a lot of processing density
in very confined spaces on little energy, even parasitic, for IOT,
in something you can possibly manufacture and control production of, at a good price.
It is a natural alternative to FPGAs. GA would be better to look into that.

EP32 is part of my Forth Bookshelf, so I know it
https://www.amazon.co.uk/Juergen-Pintaske/e/B00N8HVEZM
and
https://www.amazon.co.uk/gp/product/B071D3XMPS/ref=dbs_a_def_rwt_bibl_vppi_i18

At the moment I try to find out about the costs and have a route from VHDL to silicon.
Which design is then used is a separate decision.
Based on costs and availibility
There might be many options people here can suggest.
And Berd's design I know a little bit about.
I have asked him if it could be used as one option.

One name option I have chosen already: AIR FORTH 1 - An Intelligent RISC FORTH chip number 1
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