A new episode of "Back&Forth" has been uploaded (22Jan23)

[Hans Bezemer]

You can watch it at: https://youtu.be/i8HtlcsuKnE

This time, a string stack is added to the preprocessor - let's see how that works out..

And we replay a macro.

Hans Bezemer

[Hugh Aguilar]

You don't know what COW (copy-on-write) is.
You are copying entire strings for words such as DUP and OVER.
With my STRING-STACK.4TH I just copy pointers.
The strings don't get copied until (and if) copying them is necessary.
Most of the time, my strings never get copied because they get consumed.
Your SWAP was hilarious! Doing four string copies is retarded!

You didn't know what Harvard Architecture is either. You think that segmented memory
is Harvard Architecture. That is retarded!

You are publicly disgracing the entire Forth community with these "Back & Forth" videos
in which you represent yourself as being an expert on Forth programming.
The comp.lang.forth community disgraces themselves because they accept your idiotic
videos and they never point out your gross ignorance of the subjects that you lecture on.
This is why real programmers in the real world consider the Forth community to be
nothing more than birds chirping in the forest --- not programmers at all.
Your chirping in your "Back & Forth" videos is just meaningless and idiotic nonsense.

[Hans Bezemer]

On Monday, January 30, 2023 at 4:56:37 AM UTC+1, hughag...@gmail.com wrote:
> You don't know what COW (copy-on-write) is.

How do you know?

> You are copying entire strings for words such as DUP and OVER.
> With my STRING-STACK.4TH I just copy pointers.
> The strings don't get copied until (and if) copying them is necessary.
> Most of the time, my strings never get copied because they get consumed.
> Your SWAP was hilarious! Doing four string copies is retarded!

I got three implementations of a string stack. The first one copies pointers as
well. Sometimes things are just "good enough".

> You didn't know what Harvard Architecture is either. You think that segmented memory
> is Harvard Architecture. That is retarded!

No arguments - no discussion. Learn that.

> You are publicly disgracing the entire Forth community with these "Back & Forth" videos
> in which you represent yourself as being an expert on Forth programming.

No arguments - no discussion. Learn that.

> The comp.lang.forth community disgraces themselves because they accept your idiotic
> videos and they never point out your gross ignorance of the subjects that you lecture on.

Their problem, not mine.

> This is why real programmers in the real world consider the Forth community to be
> nothing more than birds chirping in the forest --- not programmers at all.

No arguments - no discussion. Learn that.

> Your chirping in your "Back & Forth" videos is just meaningless and idiotic nonsense.

Everybody is entitled to their opinion.

So, now what about that evil compiler that deliberately wrecks your code where the discussion
began with? I suppose this was the end of your rant. Are you calmed down now? Can
we have a decent discussion?

Hans Bezemer

[Zbig]

> > You didn't know what Harvard Architecture is either. You think that segmented memory
> > is Harvard Architecture. That is retarded!
> No arguments - no discussion. Learn that.

But if I'm correct Harvard Architecture was mainly about ability to
speed-up execution by simultaneous access to code and the data
it uses. So the separation of code and data space was the mean
rather than goal, and it's done on hardware level.
Of course it's not a crime using that term for your solution, but rather
„with tongue in cheek”.

[dxforth]

According to the Wikipedia article (which 4tH cites):

"The term originated from the Harvard Mark I relay-based computer, which
stored instructions on punched tape (24 bits wide) and data in electro-
mechanical counters. These early machines had data storage entirely
contained within the central processing unit, and provided no access to
the instruction storage as data. Programs needed to be loaded by an operator;
the processor could not initialize itself."

ISTM unless one is still using relays, punched tape and electro-mechanical
counters, the term 'Harvard architecture' could apply to any system where
there exists:

"separate storage and signal pathways for instructions and data"

whichever way one chooses to define that.

[Zbig]

> ISTM unless one is still using relays, punched tape and electro-mechanical
> counters, the term 'Harvard architecture' could apply to any system where
> there exists:
>
> "separate storage and signal pathways for instructions and data"
>
> whichever way one chooses to define that.

Possibly. What I was talking about is, for example, described on that
page: https://eng.libretexts.org/Bookshelves/Electrical_Engineering/Electronics/Implementing_a_One_Address_CPU_in_Logisim_(Kann)/01%3A_Introduction/1.03%3A_Von_Neumann_and_Harvard_Architectures

„…the major issue involved in deciding which architecture to use is that some
operations have to access memory both to fetch the instruction to execute,
and to access data to operate on. Because memory can only be accessed
once per clock cycle, in principal a Von Neumann architecture requires at least
two clock cycles to execute an instruction, whereas a Harvard architecture
can execute instructions in a single cycle.

The ability in a Harvard architecture to execute an instruction in a single
instruction leads to a much simpler and cleaner design for a CPU than
one implemented using a Von Neumann architecture.”

I read something like this before in microcontroller-related books, so I thought
it's a requirement for „true Harvard architecture”.

[none albert]

In article <f9bdc635-c29b-4ef2...@googlegroups.com>,

Zbig <zbigni...@gmail.com> wrote:
>> ISTM unless one is still using relays, punched tape and electro-mechanical
>> counters, the term 'Harvard architecture' could apply to any system where
>> there exists:
>>
>> "separate storage and signal pathways for instructions and data"
>>
>> whichever way one chooses to define that.
>
>Possibly. What I was talking about is, for example, described on that
>page: https://eng.libretexts.org/Bookshelves/Electrical_Engineering/Electronics/Implementing_a_One_Address_CPU_in_Logisim_(Kann)/01%3A_Introduction/1.03%3A_Von_Neumann_and_Harvard_Architectures
>
>„…the major issue involved in deciding which architecture to use is that some
> operations have to access memory both to fetch the instruction to execute,
> and to access data to operate on. Because memory can only be accessed
> once per clock cycle, in principal a Von Neumann architecture requires at least
> two clock cycles to execute an instruction, whereas a Harvard architecture
> can execute instructions in a single cycle.

This is clearly nonsense in view of register/register operations.

>The ability in a Harvard architecture to execute an instruction in a single
> instruction leads to a much simpler and cleaner design for a CPU than
> one implemented using a Von Neumann architecture.”

The cleanest and simplest design of a computer is a universal Turing machine.
It is clearly a von Neumann architecture.

>I read something like this before in microcontroller-related books, so I thought
>it's a requirement for „true Harvard architecture”.

The Harvard architecture is not clean, because you cannot get a program
into the computer, unless you go beyond the Harvard architecture.
You use external hardware, Intel segment cludges, EPROM programmer, or
virtual memory trickery.
(A normal c-program is a forced Harvard architecture on a
linux/microsoft/apple host machine with virtual memory. Once the
program runs, it cannot access the memory where the program resides
unless for fetching instructions. )

Groetjes Albert
--
Don't praise the day before the evening. One swallow doesn't make spring.
You must not say "hey" before you have crossed the bridge. Don't sell the
hide of the bear until you shot it. Better one bird in the hand than ten in
the air. First gain is a cat spinning. - the Wise from Antrim -

[Zbig]

> > once per clock cycle, in principal a Von Neumann architecture requires at least
> > two clock cycles to execute an instruction, whereas a Harvard architecture
> > can execute instructions in a single cycle.
> This is clearly nonsense in view of register/register operations.

…still this exactly what microcontroller-makers declare:
„AVR microcontrollers (MCUs) can execute most of instructions in single machine cycle too, but one machine cycle takes only one clock cycle.” https://simple.wikipedia.org/wiki/Atmel_AVR

[none albert]

In article <f4a70882-9dcb-4534...@googlegroups.com>,

With all due respect, but you misunderstood this article.
It highlights a significant progress going from the AVR to the 8051
regard speed. You can argue that going to a Harvard architecture
contributes to it, but the main reason is general progress.

[Zbig]

> >> > once per clock cycle, in principal a Von Neumann architecture requires at least
> >> > two clock cycles to execute an instruction, whereas a Harvard architecture
> >> > can execute instructions in a single cycle.
> >> This is clearly nonsense in view of register/register operations.
> >
> >…still this exactly what microcontroller-makers declare:
> >„AVR microcontrollers (MCUs) can execute most of instructions in single machine cycle too, but one machine cycle takes only one clock cycle.”
> >https://simple.wikipedia.org/wiki/Atmel_AVR
> With all due respect, but you misunderstood this article.
> It highlights a significant progress going from the AVR to the 8051
> regard speed. You can argue that going to a Harvard architecture
> contributes to it, but the main reason is general progress.

What I was talking about was that they stated: „AVR microcontrollers

(MCUs) can execute most of instructions in single machine cycle

too, but one machine cycle takes only one clock cycle.” — which
you've described as „clearly nonsense”.

[Zbig]

> With all due respect, but you misunderstood this article.
> It highlights a significant progress going from the AVR to the 8051
> regard speed. You can argue that going to a Harvard architecture
> contributes to it, but the main reason is general progress.

„the Harvard architecture, which is used by the AVR, uses entirely
separate buses and memories for program and data memory.
This allows for higher performance”
( https://blog.jcole.us/2010/07/17/architecture-of-the-avr/ )
„Harvard style machines allow program steps to be fetched at the
same time as data, thereby creating potentially faster through-put
and less of a bottle-neck.”
( https://maker.pro/forums/threads/avr-von-neumann-vs-harvard-architecture.64206/ )
„in the simplest version of the architecture the program fetching unit
can be busy fetching the next instruction in the program sequence in
parallel with data transfer operation that may have been part of the
previous program instruction”
( https://electronics.stackexchange.com/questions/56864/how-does-the-harvard-architecture-help )

If none of the above means „contribution to execution speed by going to Harvard
architecture” then I'm ready to agree that I don't understand what I read.

[dxforth]

I similarly held the view 'Harvard' was intended as an improvement ... until I
read the Wikipedia article. While I don't see popular opinion/use of the term
abating any time soon, it doesn't mean I need to give it support - or for that
matter, be instrumental in its downfall. Pouring an occasional bucket of cold
water seems about right for me and conserves energy.

[JKN]

I am working with a configurable CPU which can have separate, or unified,
Instruction and Data memories. Similarly, the C compiler can be configured
to target Harvard or non-Harvard architectures.
One supposed advantage of compiling for Harvard is that apparently the
resulting code size is smaller. And (as mentioned elsewhere) you can take
advantage of different memory access speeds etc.

So as I see it it, it is more 'horses for courses', than either having a
definitive advantage.

J^n

[none albert]

In article <7c4eedb9-83d1-414b...@googlegroups.com>,

I was not clear about what I called nonsense:
the statement that an 8051 could not perform one instruction in one
machine cycle. For performing one instruction you need not an
extra memory access besides the instruction fetch.
An example would be a register / register operation.

[none albert]

In article <nnd$5989905a$31fdf8f4@09b0acc25eeb8e32>,

none) (albert <albert@cherry.> wrote:
>In article <7c4eedb9-83d1-414b...@googlegroups.com>,
>Zbig <zbigni...@gmail.com> wrote:
>>> >> > once per clock cycle, in principal a Von Neumann architecture requires at least
>>> >> > two clock cycles to execute an instruction, whereas a Harvard architecture
>>> >> > can execute instructions in a single cycle.
>>> >> This is clearly nonsense in view of register/register operations.
>>> >
>>> >…still this exactly what microcontroller-makers declare:
>>> >„AVR microcontrollers (MCUs) can execute most of instructions in single machine cycle too, but one machine cycle takes only one clock cycle.”
>>> >https://simple.wikipedia.org/wiki/Atmel_AVR
>>> With all due respect, but you misunderstood this article.
>>> It highlights a significant progress going from the AVR to the 8051
>>> regard speed. You can argue that going to a Harvard architecture
>>> contributes to it, but the main reason is general progress.
>>
>>What I was talking about was that they stated: „AVR microcontrollers
>>(MCUs) can execute most of instructions in single machine cycle
>>too, but one machine cycle takes only one clock cycle.” — which
>>you've described as „clearly nonsense”.
>
>I was not clear about what I called nonsense:
>the statement that an 8051 could not perform one instruction in one
>machine cycle. For performing one instruction you need not an

This must clearly be, sorry.
>instruction cycle. For performing one instruction you need not an

[Hugh Aguilar]

On Monday, January 30, 2023 at 8:39:54 AM UTC-7, none albert wrote:
> (A normal c-program is a forced Harvard architecture on a
> linux/microsoft/apple host machine with virtual memory. Once the
> program runs, it cannot access the memory where the program resides
> unless for fetching instructions. )

Albert van der Horst doesn't know what Harvard Architecture is either!
He also thinks that when a compiler separates code and data into different
sections of memory this is Harvard Architecture.
The idea that software somehow creates a "forced Harvard Architecture"
is hilarious! Harvard Architecture is a characteristic of the processor hardware.
In a Harvard Architecture processor (such as the MiniForth), code and data
each have their own address bus and data bus, so it is possible to access
data memory concurrently with fetching the next instruction of code.

Albert van der Horst has already publicly admitted to being a Wikipedia editor.
https://groups.google.com/g/comp.lang.forth/c/qqlp1gZnVic
Normally Wikipedia editors use a pseudonym to hide their real identity
because it is such a shameful business to pretend to be experts and educators
on subjects that they know nothing about. On comp.lang.forth we have fake
experts such as Hans Bezemer and Albert van der Horst who really know
nothing about the subjects that they educate the world on, but they are either
too dumb to realize that they are disgracing themselves in public, or they
feel so proud of their political-correctness status on comp.lang.forth
that they get a thrill out of making a spectacle of their stupidity and getting away
without any criticism. John Passaniti was in this latter category.

[Hans Bezemer]

Pal, you have to learn five things:
(1) If you want to enter a discussion, you have to address the arguments you
opponent puts forward;
(2) If you pose a proposition, you have to back it up with evidence;
(3) Without any supporting arguments you're merely venting an opinion - and
that is something that has zero value - you can just shrug it off;
(4) Ad hominem attacks - that's a well known logical fallacy - zero value;
(5) Running gags only work in comedy.

Hans Bezemer

[JKN]

and almost fanatical devotion to the pope - oh, hang on, wrong newsgroup...