> On Thu, 12 Oct 2023, 11:18 Lorem Ipsum, <
gnuarm.del...@gmail.com> wrote:
> > On Wednesday, October 11, 2023 at 10:42:08 AM UTC-4, S wrote:
> > On Tuesday, August 29, 2023 at 5:09:56 AM UTC+10, Lorem Ipsum wrote:
> > > On Monday, August 28, 2023 at 6:54:43 AM UTC-4, S wrote:
> > > > On Wednesday, August 23, 2023 at 3:11:25 PM UTC+10, Lorem Ipsum wrote:
> > > > > On Wednesday, August 23, 2023 at 12:15:40 AM UTC-4, S wrote:
> > > > > > On Wednesday, August 23, 2023 at 5:22:50 AM UTC+10, Lorem Ipsum wrote:
> > > > > > > On Tuesday, August 22, 2023 at 3:57:33 AM UTC-4, S wrote:
> > > > > > > > On Tuesday, August 22, 2023 at 5:16:02 AM UTC+10, Lorem Ipsum wrote:
> > > > > > > > > On Monday, August 21, 2023 at 3:02:58 PM UTC-4, S wrote:
> > > > > > > > > > On Tuesday, August 22, 2023 at 3:41:50 AM UTC+10, Lorem Ipsum wrote:
> > > > > > > > > > > On Monday, August 21, 2023 at 1:04:38 PM UTC-4, S wrote:
> > > > > > > > > > > > On Sunday, July 23, 2023 at 3:10:24 PM UTC+10, yeti wrote:
> > > > > > > > > > > > > Dave McGuire <
mcg...@lssmuseum.org> writes:
..
> > > > Your assumption is wrong. Personally, I think the design is fatally flawed and can not be "fixed". To be useful, multiprocessor designs require much more means of communications than simple neighbor connections can provide. I don't design multiprocessor designs, because I don't need billions of operations per second. If I do need very high performance processing, it would be for a specific application, and I would design custom processing for that in the FPGA.
> > Good on you, but I've explained many times not doing what you are accusing me of, and have direct node addressing and simple multiple busses that answer your concerns. I'm hardly going to make things the same to change them. But, I'm a lowly fool, what would I know.
> What have I accused" you of exactly?
?? You just did it again. Accuse me of accusing you of accusing me about something you say you aren't accusing me of again, but are (accusing). So confusing!
Of course it's accusing me of wanting to increase speed and not enhance the architecture past complex simple neighbour to neighbour come protocol.
> This is one of the reasons it's difficult to discuss anything with you. You talk in very abstract terms, so that I can't tell what you are reffering to.
It's called intelligence. I see what is happening, you can't keep up with the level of abstraction intelligence. That's the level of intelligence you need to really understand design improvements, well design. It's pointless trying to point out things to people without that. Without that you can't really understand what is more right. It's true like tyr bird who flies over the moon in its imagination, be sure it sees it's far and flies far and comes down again. All the other birds with it, think it's great he flew over the moon. Mean while the bird in the tree from another direction says he didn't fly over the moon, he just went upon the air. The birds sharing the delusion can not understand this, and say the wise bird in the tree is wrong. And the bird in the tree says, then how can they understand his design for a plane.
> The "assumption" I say is wrong, is the idea that every problem can be "fixed". There are fundamental limitations to any issue.
Which is wrong here.
> > >> > ..
> > > > > The Transputer CPUs are the only other ones I know of, that had anything like the GA144 communication connections. They were essentially serial connections, with a similar
> > >> > I had suggested they change that to a parallel connection. I thought they had announced talked about that.
> >> > Which has nothing to do with the issue of connectivity. The issue is not bandwidth, it's connections. Look up what a hypercube is. That is a structure that is useful for this. But, it still gets out of hand as the numbers of processors goes up. The real estate goes up ***HUGELY***. It's not workable. The GA144 isn't the first multiprocessor design ever attempted
> >> I did not realise, you don't design these systems.
> I don't design what systems??
What you were saying you don't design before.
"I don't design multiprocessor designs, because"
> Well, it's simple, you program down to the capabilities of the hardware. For my graphics processing unit, I couldn't resolve the design to be as useful as I wanted due to bandwidth constraints. Higher bandwidth would definitely solve everything, especially to external memory, with direct execute. Simple example. I could outline an elaborate structure to use the resources passing the data along and inserting data as it goes, but I was practically better off if I did most of it with just one processing node from external memory with execute The problem is, that raises production costs. But, the modifications go beyond that into treating groups of processors as sections that pass and receive data wherever it is needed. Careful embedded programming means you avoid choking the data path. As is, the chip suites low energy data passing and modification applications, as long as you don't try to get too ambitious and do something else, you should be fine. But, except for my graphics processor, sound, maybe something to do with storage and laser vector projection, that's not really me. I want what most of you do, flexible access and use, but that's not what this chip was aiming for, very low-end stream processing alternative to fpga's, at lower energy and cost. The feature set modifications to make it more useful generally, are very simple.I have often said, to have at least one processor as normal, able to use the array for extra processing and IO. My non blocking IO structure would make using the array for random access or neighbour, a cinch. Lots of objections solved. If you want to go up a few levels to a hypercube, go and buy one. I know that emulation of hypercube at low energy and reasonable speed (bandwidth plus the messaging improvements), is probably better. It ultimately is cheaper with lower energy and cost per unit of performance. Most applications do not require a full hypercube design, so there is a market underneath hypercube systems, as we regularly use. My previous old way of dividing up the work space, for my own design, is very different than normal. But, you can't get much improvement if you don't change things. The stuff I'm proposing for the GA, is just simple feature improvements using low hanging fruit.
> Once you have a design description of this, let me know. I would be interested in funding an approach. But, it would require a clear, solid design approach.
Well thank you. If we had been more collaborative on approaches, I'm sure we could have done something. I'm looking at moving most of it all onto my home made chip alternative technology, then maybe out to Arduino and Pi like products and manufacturing. I have to see how well I can get that to work with partners. How many MHz, or if it's going be a (X)tz slow.
> > > > handshake to the GA144. That also did not catch on very much.
> > > > So, you don't support butted processor to processor parallel ports, and changing the hand shaking environment? That's what I proposed.
> > > Let us know when you've run simulations, or built chips or at least done some calculations to show how well it would work.
> > What, you mean those things any truely intelligent person can do in their heads? Pity Cray and Tesla aren't still around.
> Yeah, it's funny, but the people who would use your designs would not understand anything you provide to explain the device.
"Truely intelligent".
IP rules. What's provided is a valid increase in data rate exchange from reduced clock cycles, with no space wastage. In matter of fact my direct to neighbouring memory write buffering speeds things a biten more. You must realise, the answer to massive device performance killing interconnects is high speed data passage to destination, as this is lower performance, low energy alternative. I'm not expecting hypercube performance very easily. But the general and row volume and group buses allow high data passage alternatives to mass interconnects. You have to just program to the hardware model, so that you keep as much as possible to neighbours, then in row and column common bus, and between groups, if the application allows. As this then frees up the global row, column and group busses as much as possible to avoid conflicts. You will get additional communications delays than going directly on the global bus, but you view it as pipe lining, and your aim is lowest energy per unit of computation at a modest processing load, so it is ok. I could design a global to global distributed parallel system using different technologies. Which might be worth doing on a quantum level using the architecture I was planning for the descent system.
..
> > Why follow me around in my threads?
> I thought we have conversations, but you seem to think of my comments as rude or attacks. Why do you respond to me at all? Do you have a mental condition that you can't ignore my comments?
I think you find other people commenting on your posts too.
My threads or comments, that you just have to write to, in funny ways, that need clarification. Why do you keep coming and saying stuff, where your stuff is not wanted? So, who has the mental issues? I certainly don't have time to follow people around like a lost puppy, so it would be helpful if they didn't as well.
> Besides, this is not YOUR thread. This was started by someone else. So, if you don't like my replies, too bad.
As if that excuses you from water bombing most of my threads. Diverting attention then. When I reply to other people you don't have to follow me around. How would you like it if somebody just followed you around, sticking their head over your shoulder commenting to people?
> > > > > > > > > That you don't have to try to use 700mips, and every cycle you use is more or less an minimal on actual work/communications, compared to everything both of us complain about in performance and programmability.
..
> >
> > The idea is to run more data and instructions from the external interface. Fur my sequential data application, like a massive pipeline, speed helps. But, it's those general purpose processing modifications I need most. If only they had 512 words of sram per data node too, or 256MWord each, I could do Nintendo GBA/SNES like tricks with some 3D too.
> The external interface will always be limited by the external interface. That's a major limitation in every high speed computing device, the memory interface, or the I/O interface. Internal processing can be increased by increasing the number of processors. But, the ultimate limitation is either internal comms or external comms, because they can not keep up with the number of processors.
What we are talking about here, is to reduce communications cycles freeing up cycles for processing work load, and increasing the rate of transmission, to allow processing load to be maximized. This increases external memory access and internal communications data access, to increase performance availability, while simplifying programming for similar to 5% more transistor counts plus whatever extra memory. As I've said before, we are better to put each processor in a sea of memory for heat dissipation, if we want to run them at high speed on normal silicon architecture.
> > > > I did talk about redesigning the architecture as a major improvement in performance, then you can afd speed, which the redesign could handle, which is a seperate issue. Maybe you should just open source all your military designs,
> > > LOL!!! I don't know what "afd speed" means. You can open source anything you want.
> > You known what I meant.
> No, I don't know what "afd speed" means.
And speed. See intelligence. "LOL..". It's good to avoid laughing at your own jokes? :)
> > Open source, I was previously only aiming to open source certain things
> > >
> > > What "military" designs are you talking about? You seem to have gone off the deep end on this. When did I say anything about military designs?
> > You told us you get military contracts. Why waste time?
> I've never said I get military contracts. Please find a single post where I did say that.
Well, how does the military order products from you? No contract of sales, or terms of supply?
> > > > you like trying to get others to spill their IP, but what about giving your IP away for free, instead.
> > > Why are you being a troll?
> > Because I'm not, but you are often doing so. A troll acts stupid and makes mistakes, in order to bait a response.
> No, a troll simply makes posts to get an inflammatory response. I'm trying to get straight answers out of you. That is very hard to do.
No, you get answers more than you deserve, and you just keep going. It's not up to us to teach you respect for intelligence. We got better things to do. If you are really lacking in the abstract intelligence you make out, then either: Figure it out yourself (as you have wasted enough), or don't say anything and take it as is beyond your imagination.
> > > > > > Thank you Rick Collins. How are things at Artemis, you were working on a new FPGA Misc design? Why don't you start a thread and talk about that. Sounds very interesting, well it would be to me, I take interest in a number of different things, and people.
> > > > > I don't do MISC designs for no reason. I am ..
> > > Nice talking to you.
> > Thank you very much for that.
> It's a shame I can't get logical comments from you as easily as you make inflammatory comments.
So, I speak higher logic to you. You act like you don't understand higher logic. Haphazardly challenging and knocking it in an offensive way, looking for an response, so you can then act like isn't warranted, and continue. We will see.