"A Review of Soft Core Forth Processors" slides

[Christopher Lozinski]

Here are the slides for my upcoming talk "A Review of Soft Core Forth Processors".

https://pythonlinks.info/presentations/ForthPresentation.pdf

I will be giving the talk at the August SVFIG meetup, and at the Stocklolm FPGA World conference in September. Your expert comments would be most appreciated.

For those who do not like the term "Forth Processor", I define it as a stack machine running programs written in Forth.

The general plan is to build large numbers of MeCrips cores on an FPGA. A future posting will discuss the details.

Thank you for all the advice I have received here so far.
Christopher Lozinski

[Jurgen Pitaske]

Thank you very much for sharing your presentation.
The first reactions I had:

Can you please add Bernd Paysans b16
https://bernd-paysan.de/b16.html

And can you please add a page or 2 with links, so people can find the places more easily.
You have done so much work putting it all together - please share the links.

And it might be worth mentioning, that there are (or were)to my knowledge 2 Forth Processors in production/products
the b16
the J1

[Jurgen Pitaske]

And please remember the book about Ting's EP32
https://www.amazon.co.uk/EP32-RISC-Processor-Description-Implementation-ebook/dp/B071D3XMPS/ref=sr_1_12?qid=1690962051&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-12

[Jurgen Pitaske]

And the TTL Processor Brad described in this book
https://www.amazon.co.uk/Moving-Forth-Internals-TTL-Processor-ebook/dp/B07BTV7QVR/ref=sr_1_11?qid=1690962051&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-11

[Hugh Aguilar]

On Wednesday, August 2, 2023 at 12:19:13 AM UTC-7, Jurgen Pitaske wrote:
> And it might be worth mentioning, that there are (or were)to my knowledge
> 2 Forth Processors in production/products
> the b16
> the J1

The MiniForth processor was used in the motion-control board of the
laser-etcher in 1995. In a laser-etcher, the mirrors have to move at a steady
speed. They can't have a pause when they change direction because this
will result in a burned blotch at the point where the direction changes.
The speed has to be consistent whether the lines are ziggy or straight.
This requires a very high-speed processor!
The B16, J1, Mecrisp-Ice, BUGS18, RTX-2000, etc. are toy processors
that are not capable of supporting motion-control in the year 2023,
although the MiniForth did this in 1995.

I'm proud of having written MFX the assembler/simulator and Forth
cross-compiler for the MiniForth, although Tom Hart and Juergen Pintaske
will never admit that I wrote MFX. The liar Tom Hart says:
https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0/m/mvVy-GN7AwAJ

> [Hugh] was difficult to work with. ...
> I let him go myself...
> He had nothing to do with the processor itself,
> that was all designed by John Hart and Steve Brault.
> The PLD version [of the MiniForth] was based upon our original Forth Engine
> done long before we ever ran across Hugh.

Tom Hart is not giving me credit for writing MFX that is an integral aspect
of the MiniForth (a processor is not worth anything without an assembler).
He is not giving me credit for being an assembly-language programmer.
John Hart didn't know how to write the assembler. The advice that he gave
me was useless and really absurd. I doubt that Steve Brault knew how to write
the assembler either --- he was already employed at Testra, so if he knew how
to write the assembler, then why did they need to hire me to do it? --- Steve had
to wait for me to write the assembler before he could begin porting his
motion-control program (I remember that he was quite impatient waiting).
I figured out how to do the out-of-ordering of the instructions myself.

> Sounds like the Forth community has some problems with non team players.

The problem with the Forth community is not a lack of team players.
Juergen Pintaske is the most loyal team player than any big boss could
possibly hope for --- Stephen Pelc will certainly vouch for this statement!
The problem with the Forth community is too many liars --- and too many
brown-nosers who support the leadership unquestioningly.

Which team does Tom Hart think lacks team players?
Obviously, he is referring to the Forth-200x committee!
I think that, with his nasty email attacking me, Tom Hart was brown-nosing
Stephen Pelc in the hopes of getting appointed to the Forth-200x committee
so he could be a big leader too (the whole point of joining a team
is to quickly get promoted into leadership).

[Jurgen Pitaske]

BLAH BLAH BLAH - your usual bullshit.
We cannot verify any of your bullshit.
And actually we do not care I assume.
A taxi driver and plummer being the best Forth programmer?
What a hilarious joke.
Please do not masturbate on CLF so openly.

[Lorem Ipsum]

One of the issues with such presentations using viewgraphs (sorry for the ancient terminology) is when they are so terse, they themselves contain virtually no information. Some of yours are like that. Brevity is good, but at some point you need to have them convey some information, without the presentation. I like to use them as review material after I've heard such a presentation. Without a bit more info, they aren't much good for that.

The slide labeled "What is Forth?" seems to be showing RPN. That's not what Forth is about. Is that really all you wish to say about Forth as opposed to other languages?

Much of your presentation treats Forth and stack CPUs as if they are joined at the hip. On the page, "Why Forth/Stack Machines?", you show the MicroBlaze compared to the J1 and MicroCore. How are each programmed? I expect the MicroBlaze was programmed in C? Why not program it in Forth? Then it would be comparing Forth on a register machine vs. Forth on a stack CPU.

The list of "Forth Systems" and "70 Soft Core Forth Processors" would seem to point to a weakness of Forth, rather than a strength. Why are so many implementations needed? Most people won't know this, but most of the Forth systems and CPU designs are not very well completed, or supported. They are mostly hobby projects.

When you talk about the "EP16/24/32/64", you say, "No traction", but no explanation. This is an important point. It would be great to note why.

For the "MicroCore", you say "Runs everywhere". What does that mean??? Why would a soft core CPU not run everywhere?

For the "J1", you say "But very limited". Limited how???

Under "e4thcom" you might mention it is only Linux and OSX, but no Windows support.

Why no mention of the F18A or GA144? It's hard to get more Forth like than that.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

[Brian Fox]

On Thursday, August 3, 2023 at 5:59:42 AM UTC-4, Lorem Ipsum wrote:

> One of the issues with such presentations using viewgraphs (sorry for the ancient terminology) is when they are so terse, they >themselves contain virtually no information. Some of yours are like that. Brevity is good, but at some point you need to have them >convey some information, without the presentation. I like to use them as review material after I've heard such a presentation..

>Without a >bit more info, they aren't much good for that.

On the other hand using a "power point" style slide show is not the message.
The presenter conveys the message. Slides are for support.

I have too often had junior people try to take me threw "wall of text" slide shows.
My opinion is a separate handout document with the detail is better than putting it on the screen.

I took a course from an company called Black Isle where they want a cover slide on the screen
while you are speaking. Then the presenter says "Here is an example of what I am talking about" or
some such line and then says nothing while the slide is being read by the audience.
After a proper time, the slide comes down and the speaker resumes.

Theory being that we cannot read a slide and hear a speech at the same time.

It's very effective when done well, but it drove our CMO nuts when I did it because he
wanted to read ahead. :-)

[Lorem Ipsum]

On Thursday, August 3, 2023 at 3:36:43 PM UTC-4, Brian Fox wrote:
> On Thursday, August 3, 2023 at 5:59:42 AM UTC-4, Lorem Ipsum wrote:
>
> > One of the issues with such presentations using viewgraphs (sorry for the ancient terminology) is when they are so terse, they >themselves contain virtually no information. Some of yours are like that. Brevity is good, but at some point you need to have them >convey some information, without the presentation. I like to use them as review material after I've heard such a presentation..
> >Without a >bit more info, they aren't much good for that.
> On the other hand using a "power point" style slide show is not the message.
> The presenter conveys the message. Slides are for support.

Which is my point, "support" should include being useful after the presentation. A good set of viewgraphs is a good balance between too little and too much information.

> I have too often had junior people try to take me threw "wall of text" slide shows.

People can always screw up anything. Your aversion is likely from such bad presentations.

> My opinion is a separate handout document with the detail is better than putting it on the screen.

That's not actually so good. The material in a second handout is not going to be read during the presentation and is not likely to be read after. A single, well written presentation is worth its weight in gold, even if it's all electronic.

> I took a course from an company called Black Isle where they want a cover slide on the screen
> while you are speaking. Then the presenter says "Here is an example of what I am talking about" or
> some such line and then says nothing while the slide is being read by the audience.
> After a proper time, the slide comes down and the speaker resumes.
>
> Theory being that we cannot read a slide and hear a speech at the same time.

What is the difference between theory and practice?

> It's very effective when done well, but it drove our CMO nuts when I did it because he
> wanted to read ahead. :-)

Everyone learns differently. That's the reason for having the viewgraphs in the first place. Otherwise it could just be a speech. Good viewgraphs are worth putting some time into. Empty viewgraphs are worth the effort they didn't take to generate.

To each their own. I just know that several of the pages in this presentation were essentially devoid of content. From page 2 of this presentation, I would have no idea what was the answer to the question, "What is Forth?" once the presentation was a month or two in the past. Hopefully the answer is not "a stack based language".

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

[Jurgen Pitaske]

On Wednesday, 2 August 2023 at 07:31:00 UTC+1, Christopher Lozinski wrote:

I have reposted it in the Forth facebook group,
and people can send you an email
as well as you have your email address in your presentation
lozi...@PythonLinks.info <lozi...@PythonLinks.info>;

[Jurgen Pitaske]

For people who might not know where to find this group on facebook
https://www.facebook.com/groups/PROGRAMMINGFORTH

[Christopher Lozinski]

Thank you for the feedback.

I was just doing this for my own education. I had not realized that this document would be more widely useful.

I will go ahead and incorporate your suggestions, and repost it.

I think that you are quite right, that the slides do not stand alone. But then the video takes too long to watch. I should draft a script on Google Docs, and allow people to edit it. I am sure that some of my beliefs are incorrect, or incomplete. And many links are included, most of the titles are actually hyperlinked, but since there is no underlining you cannot tell. I will also fix that.

Warm Regards
Christopher Lozinski

[Jurgen Pitaske]

Thank you very much for updating your hard work, and sharing it as well.

[Jurgen Pitaske]

On Friday, 4 August 2023 at 07:39:35 UTC+1, Jurgen Pitaske wrote:

A first feedback on facebook:

Jose Morales

Here is a 'NEW WIP Forth CPU" https://github.com/jemo07/MyFPGA_FORTH, I would not add it to the list, just saying there is great deal of interest ( IMO ) of this subject, so looking forward to more details of the talk. There is a one missing that might be of great interest, Ilya Tarasov (sorry for the spelling if I goofed that) who had a well advanced Forth FPGA CPU, might we well worth the trouble to add it to the presentation.
Here are some areas where I believe the presentation could provide more details on the Forth CPU's with some of the questions that would otherwise be answer in such a subject.
Architecture and Design
What is the architecture of the Soft Forth CPU? How does it differ from traditional CPU architectures?
Why choose a stack-based architecture? What are the advantages and disadvantages?
How is the instruction set designed? What considerations were made in selecting specific instructions?
Implementation Details
How is the Soft Forth CPU implemented on an FPGA? What are the specific Verilog or VHDL constructs used?
What are the optimization strategies employed? How are resources like gates, memory, and clock cycles optimized?
How is the stack implemented and managed? What are the mechanisms for stack overflow and underflow handling?
Performance and Benchmarking
How does the Soft Forth CPU perform compared to other soft CPUs or traditional hardware CPUs?
What are the benchmarks used to evaluate performance? How does it perform in terms of speed, resource utilization, power consumption, etc.?
Applications and Use Cases
What are the specific applications or domains where a Soft Forth CPU would be particularly beneficial?
How can the Soft Forth CPU be integrated into existing systems or workflows?
Challenges and Limitations
What are the challenges faced in designing and implementing a Soft Forth CPU?
What are the current limitations, and how might they be overcome in future iterations or versions?
Future Directions and Research
What are the future directions for Soft Forth CPUs? Are there new features, optimizations, or applications on the horizon?
How does the Soft Forth CPU fit into the broader landscape of research and development in soft CPUs and FPGA technology?

https://github.com/jemo07/MyFPGA_FORTH?fbclid=IwAR25E36dumZPqnrIrypOstcKqS8kdRoQJBVnrjWkSf_GOSjuWQgUGfa_aRg

[Hugh Aguilar]

On Tuesday, August 1, 2023 at 11:31:00 PM UTC-7, Christopher Lozinski wrote:
> Here are the slides for my upcoming talk "A Review of Soft Core Forth Processors".
>
> https://pythonlinks.info/presentations/ForthPresentation.pdf
>
> I will be giving the talk at the August SVFIG meetup, and at the Stocklolm
> FPGA World conference in September.
> Your expert comments would be most appreciated.

Presenting slide shows and giving talks at conferences makes you look
like a sales clown, because this is what sales clowns do.
Nobody will ever believe that you are a programmer after they have seen
you playing the sales clown.

If you want to be a sales clown, then just promote MPE --- maybe Stephen Pelc
will eventually give you a commission --- but promoting multiple internet freebies
such as MeCrisp Ice is a waste of time because there is no commission for freebies.
Stephen Pelc has a "clean-room implementation" of the RTX-2000 on an FPGA.
You could sell that for MPE! It is a useless retro processor, but it might sell
in the Forth hobbyist market as represented by comp.lang.forth.

> The general plan is to build large numbers of MeCrips cores on an FPGA.

I assume that you mean Matthias Koch's MeCrisp-Ice processor.

There is loosely coupled parallelism (a multi-core system such as you are
describing), and then there is tightly coupled parallelism (the MiniForth).
With tightly coupled parallelism, you read and write to registers concurrently.
This is why the MiniForth was fast. It could pack up to 5 instructions into a
single 16-bit opcode and the opcode would execute in a single clock cycle.
The 5 instructions could include an instruction that read from a register and
an instruction that wrote to that same register. This is (I am told) impossible
on an FPGA because FPGA chips lack the connectivity to support multiple
instructions that can simultaneously access (read or write) one register.

I have my TOYF design posted here:
https://board.flatassembler.net/topic.php?t=21841
This is probably not possible to implement on any FPGA.

My MFX assembler did out-of-ordering. The programmer could write his
source-code as if the instructions executed sequentially, but my assembler
would rearrange the instructions to pack them into the opcodes so that
the instructions would execute concurrently but would do the same thing
as if they executed sequentially --- the assembler would pack the instructions
in such a way as to minimize how many NOP instructions had to be inserted.
Also, I wrote a simulator. The assembler would not only generate machine-code
that would run on the MiniForth, but it would also generate Forth code that
simulated this machine-code and would run on the MS-DOS host. This is
very fast! This is fast because the simulator doesn't have to decode the
opcodes at run-time, but all of the decoding is done at compile-time.

With loosely coupled parallelism you have multiple cores running concurrently,
but they can only communicate with each other through memory, and not
concurrently. So, if you have an eight-core system you need to have eight
unrelated tasks to do. This isn't useful in motion-control because you have
only one task to do, and you have to do it at high speed --- you need one fast
processor, not eight slow processors doing eight unrelated tasks.

For the most part, I think that multi-core systems are only useful if each core
does something application-specific and different from what the other cores
are doing. This seems to be how Ilya Tarasov's multi-core FPGA systems work.
This is not going to work for a general-purpose processor in which each core
is not customized for a specific task in the application, but all the cores are alike
and non-specialized. This is why I'm not interested in the Parallax Propeller
although I have been told by many people that this is true parallelism and
I should learn Propeller programming so I can be an expert on parallelism too.

[Jurgen Pitaske]

Christopher, please do not take this SALES CLOWN for serious.
He sometimes escapes his mental home and then starts ranting here and elsewhere..
CLF is not the only place where he does his sales pitches regarding MFX.
How much he has done there nobody really knows or cares.

He shits on anybody who does a serious job.
He cannot fasom, that he tries to sell his ideas - he just cannot grasp what he does.

Just follow the link he posted.
It is there like Slide after Slide, after slide.
His formatting lacks a bit,
but reflets his mental situation well.

Please just continue with your presentation and send an update.
You might want to include in your presentation the link to a Soft CPU people can easily replicate.
Downoad the programming file for the Core, flash it in and see the OK ...
This would possibly help.

Your Link to NANDland was great.
I assume we could convince Russel, to sell the board preprogrammed with a core - anybody can overwrite this later if wanted.
But a clean starting point for everybody.

[Christopher Lozinski]

> you look like a sales clown.
I agree with you that there is no money to be made with Forth cores, but there is tremendous knowledge to be acquired by presenting things. And better yet, connection with some very interesting people. Humans are a social species. We share knowledge. The feedback I have received from posting the slides has been fantastic. They include links to the source code on how the GA144 nodes communicate, detailed documentation on how the transputer worked, and lots of other great advice. It is only by surveying the market, that i learned how active the Mecrisp community is. And one really wants to target an installed base, or there will be no users. Let alone no software to run.

In the private discussions following posting, I realized that Video processing is a bad target market. the Low cost FPGA's are just not large enough.
640 x 480 pixels x 24 bits/pixel = 7372800 bits.
The Lattice ECP5 family has at most 3.7 Mbits of RAM.

I also learned that human sound localization is way more complicated than I had realized.
https://en.wikipedia.org/wiki/Sound_localization#:~:text=Localization%20accuracy%20is%201%20degree,of%2010%20microseconds%20or%20less
Multiple Forth cores for hearing aids will just have to wait a while.

And I did learn of a great market for a six core Forth CPU, but that will be the topic of another thread.

There is an old saying: "Be hard on issues, soft on people." When. you criticized me as a sales clown, I completely missed what is your concern with the presentation. So I did not learn anything from your email. What was the specific issue that bothered you with the presentation. Did you want it to be more technical??? Was it something else?

Warm Regards
Christopher Lozinski

[Lorem Ipsum]

You are welcome to try, but it is very unlikely you will receive anything useful from Hugh. He could contribute in significant ways, but he has... "issues" that force him to spew hatred and venom, to no useful end. We have seen this many, many times.

It is possible that you may get some cooperation from him, but eventually, you will make some mistake that he perceives as a personal insult and he will launch a tirade. End of cooperation.

Whatever. Good luck in your efforts.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

[Hugh Aguilar]

On Tuesday, August 8, 2023 at 2:18:10 AM UTC-7, Christopher Lozinski wrote:
> > you look like a sales clown.
> I agree with you that there is no money to be made with Forth cores

I didn't say that no money can be made with Forth cores.
I said that no selling internet freebies doesn't provide a commission.
Forth cores can be worth money if they are competitive in the real world.

Testra has been in business since 1995 thanks to the MiniForth
(later the RACE) Forth cores. Testra was on the verge of going
out of business in 1994 because their Dallas 80c320 motion-control
board wasn't competitive with the competition that was using an
MC68000 programmed in C --- the MiniForth board (based on the
Lattice isp1048 PLD) was less expensive than the MC68000 board
and out-performed it. This is the only case that I'm aware of in which
Forth did beat C in both price and performance. I made my MFX
assembly-language as easy to use as possible (the out-of-ordering
was done by the assembler, so the programmer could write his
assembly source-code as if the instructions executed sequentially).
Despite making MFX assembly-language as easy as possible, I would
still estimate the difficulty of MFX assembly-language to be about
an order of magnitude above MC68000 assembly-language.
For one thing, the MiniForth didn't have an ALU so there was
no instruction to do integer addition. For another thing, there was
no way to change the PC (no branch or jump instructions)
other than the NXT instruction at the end of the primitives (it was
possible to conditionally load the IP register inside of the primitive).

With processors, you get high-performance, low cost and easy programming.
Pick any two!

> there is tremendous knowledge to be acquired by presenting things.

There isn't any knowledge to be acquired by presenting things.
Educating the world on a subject that you have superficial knowledge of
is the path of the fool.

> The feedback I have received from posting the slides has been fantastic.

When you try to present information using light-weight media such as
a slide show, technical people will run away.
You end up getting fantastic feedback from non-technical people such as
Juergen Pintaske. He's a pig! Tom Hart totally disgraced himself by
accepting Juergen Pintaske as his peer --- I recommend against doing this.

[Jurgen Pitaske]

[Christopher Lozinski]

Thank you for all of the feedback. Much of it was included. Here is the new version.
https://pythonlinks.info/presentations/ForthPresentation.pdf

On page 4, I talk about the main application for Forth Processors. "System within a chip"

On page 13, I am now able to classify the different processors based on what their design goals and constraints were. It makes it much easier to choose the right processor for an application.

On pages 29-33 I talk about my plans. 1 core, 8 core and 10 core processors. Hearing aids , and FFT's.

Hyperlinks are underlined.

The GA144 was not included because it is not a soft core processor. Multiple requests for them to make it available as a soft core processor have been rejected.

Processors I had never heard about were not included.

People who were rude, got their comments ignored.

Additional comments are welcome. I will present at SVFIG later this month.

Thank you for all of the help.
Christopher Lozinski

[Jurgen Pitaske]

Quite a few nice changes.
Just a quick point: it is b16 not B1

[Brian Fox]

Looks great.

I like the shot to Forth community about your hearing aid application:

"Many older Forthers as initial users" :-)))))

Nice.