A memory barrier is needed

[Ramine]

Hello...

I have just looked at my algorithm of my scalable Asymmetric Distributed
Reader-Writer mutex, and i think it needs a memory barrier on the
reader-side, because on x86 loads of the inside reader section can be
reordered with the following store:

myid1:=0;
FCount1^[myid1].fcount1:=FCount1^[myid1].fcount1+1;

So now i think you can be more confident..

You can download my new and updated C++ synchronization objects library
from:

https://sites.google.com/site/aminer68/c-synchronization-objects-library


and you can download my updated scalable DRWLock from:

https://sites.google.com/site/aminer68/scalable-distributed-reader-writer-mutex



Thank you,
Amine Moulay Ramdane.