On 01/11/16 23:16, Rick C. Hodgin wrote:
> On Tuesday, November 1, 2016 at 5:13:08 PM UTC-4, David Brown wrote:
>> On 01/11/16 21:58, Vir Campestris wrote:
>>> On 31/10/2016 10:09, David Brown wrote:
>>>> I look to the future, and for every processor made that has efficient
>>>> traps on division by zero, there will be thousands made that don't have
>>>> such traps. There even will be thousands made that don't even have
>>>> instructions for division.
>>>
>>> I consider that unlikely. Once upon a time I used 8 bit processors that
>>> didn't have a divide; these days I use 32 bit ones with a divide, and
>>> they only cost a couple of bucks.
>>>
>>
>> There are a great many microcontrollers - including 32-bit ones - that
>> don't have hardware division instructions. Fast division is big (and
>> therefore expensive) to make in hardware, and relatively uncommon in
>> code in microcontrollers. Often when you do have division, it is by a
>> constant and can be turned into a multiplication (or even a shift). So
>> omitting hardware division is a reasonable tradeoff for the smallest and
>> cheapest devices. In terms of the number of devices produced, these are
>> the sizeable majority.
>
> I disagree with that goal.
What "goal" do you mean? I haven't mentioned any goals here, so I don't
know what you are referring to. The nearest I can think of is the goal
of making microcontrollers as small, cheap and low-power as practically
possible without compromising required functionality. And for most
small microcontrollers, that includes not adding a hardware divider.
Or do you mean that your goal for your language does not include support
for smaller devices (or even many big ARM application processors), since
they don't have hardware division instructions? And many processors
that /have/ hardware division instructions don't have traps on divide by
zero (because it is a mess to implement in hardware) - are they also to
be excluded?
> The software written for these devices is
> typically not very complex or large (due to the constraints of the
> devices). On the other hand, Android-like devices and larger have many
> Gigabytes of memory and storage, and run much larger much more powerful
> applications.
Software on small microcontrollers can be surprisingly complex. As for
"large", that depends on how you measure it - the binary image is
usually far smaller than on a PC application, but the lines of code
written for the program (excluding libraries and third-party components)
is a lot more comparable (to the extent that there is a "typical" PC
application and "typical" microcontroller application).
And yes, Android devices have bigger processors - they are not
microcontrollers, but processors. And many of them lack hardware
division instructions.
>
> It should be expected for any language designer to target a growing set
> of internal abilities exposed to it through the ISA, not less, and not
> a decreasing set.
>
No, it should be expected for a language designer to make their language
run well on any appropriate target, and even better on the more capable
targets.
So a language designed today with an aim for speed would have native
support for vector operations so that programmers can easily take
advantage of SIMD units on many larger processors. If its typical
targets included DSPs and control systems, then it might have native
support for saturating arithmetic which can be implemented very
efficiently in most DSPs and microcontrollers such as Cortex M devices.
But it would be a bad move to make saturated arithmetic the default if
the language was also to be used on x86 processors.
It is fine to take advantage of the newer features of the latest
processors - but you should think long and hard before making your
language /require/ processor features that are not universal.
And remember, the processor world spreads out in many directions - it is
not just "bigger and faster". Nor is there a consolidation in the
processor world, and it certainly is not consolidating on the feature
set of the x86 devices you are familiar with. New processor
architectures are developed all the time, and they don't follow the
legacy ideas of x86. Traps are a fine example of something you
definitely don't want to require, because they are often not supported.
It is your decision what features you will want and what targets you
expect to use, of course.
> Hardware is very cheap these days. The fact that it's still cheaper in
> the smaller form factors is of very little overall consequence because
> they have significantly lesser demands of a language, even enough that
> many of them could be handled with simple assemblers with supporting
> function call libraries provided for by the manufacturers just as
> easily as relying upon something as complex as a C standard library.
> In fact, I'd wager that in such applications the C standard library
> would be a huge hindrance due to the special needs of limited hardware
> for optimization.
I'm sorry, I can't see what you are getting at here. Maybe I haven't
had enough coffee yet.
>
>> It is changing, and a larger proportion of devices made and sold now
>> have hardware division than just a few years ago, but I still expect
>> that for every "big" cpu (like an x86) made with traps on divide by
>> zero, there are vast numbers of small microcontrollers with no division
>> support. Maybe "thousands" is an exaggeration - but certainly "lots".
>>
>> IIRC, hardware division was dropped from some members of the 68k family
>> because someone noticed that a software division loop was faster than
>> the hardware instruction!
>
> I see the future as an increasing set of abilities exposed to the
> software developer, up to a point, but always including the base and
> fundamental operations in integer and fp.
>
Well, that is definitely /not/ the future of processors and processing
units - just a future of one part of it. For higher performance, wider
is the future - not bigger, faster or more complex. Vector and SIMD
operations are getting more common - these are often simpler than the
kind of "do everything" instructions on an x86. For example, SIMD
floating point operations will often not be IEEE compliant, and they
certainly won't trap - they expect to give you sensible results for
sensible inputs, with little regard for what comes out when you put in
bad inputs. There are many processor architectures where speed comes
from tightly-coupled parallel processing - inter-process and
inter-processor communication is key. On the other hand, floating point
performance is relatively low priority (or missing altogether) in many
architectures.