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About my scalable algorithms..
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Horizon68
Feb 1, 2019, 5:04:08 PM2/1/19
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Hello,
Read this:
About my scalable algorithms..
My scalable algorithms that i have invented are working now on x86.
But i will port them smartly soon to other CPU architecture like ARM..
I think i will port just my scalable MLock and my scalable AMLock for
Delphi and Freepascal so that my scalable algorithms work on ARM CPU
architecture, ARM that is of a weak memory model, here is the Memory
ordering of ARM:
https://en.wikipedia.org/wiki/Memory_ordering
Here is my scalable MLock and my scalable AMLock that i have invented:
https://sites.google.com/site/scalable68/scalable-mlock
and here:
https://sites.google.com/site/scalable68/scalable-amlock
I think x86 is TSO and is the same as Sparc TSO.
About memory models and sequential consistency:
As you have noticed i am working with x86 architecture..
Even though x86 gives up on sequential consistency, it’s among the most
well-behaved architectures in terms of the crazy behaviors it allows.
Most other architectures implement even weaker memory models.
ARM memory model is notoriously underspecified, but is essentially a
form of weak ordering, which provides very few guarantees. Weak ordering
allows almost any operation to be reordered, which enables a variety of
hardware optimizations but is also a nightmare to program at the lowest
levels.
Read more here:
https://homes.cs.washington.edu/~bornholt/post/memory-models.html
Memory Models: x86 is TSO, TSO is Good
Essentially, the conclusion is that x86 in practice implements the old
SPARC TSO memory model.
The big take-away from the talk for me is that it confirms the
observation made may times before that SPARC TSO seems to be the optimal
memory model. It is sufficiently understandable that programmers can
write correct code without having barriers everywhere. It is
sufficiently weak that you can build fast hardware implementation that
can scale to big machines.
Read more here:
https://jakob.engbloms.se/archives/1435
Thank you,
Amine Moulay Ramdane.
Read this:
About my scalable algorithms..
My scalable algorithms that i have invented are working now on x86.
But i will port them smartly soon to other CPU architecture like ARM..
I think i will port just my scalable MLock and my scalable AMLock for
Delphi and Freepascal so that my scalable algorithms work on ARM CPU
architecture, ARM that is of a weak memory model, here is the Memory
ordering of ARM:
https://en.wikipedia.org/wiki/Memory_ordering
Here is my scalable MLock and my scalable AMLock that i have invented:
https://sites.google.com/site/scalable68/scalable-mlock
and here:
https://sites.google.com/site/scalable68/scalable-amlock
I think x86 is TSO and is the same as Sparc TSO.
About memory models and sequential consistency:
As you have noticed i am working with x86 architecture..
Even though x86 gives up on sequential consistency, it’s among the most
well-behaved architectures in terms of the crazy behaviors it allows.
Most other architectures implement even weaker memory models.
ARM memory model is notoriously underspecified, but is essentially a
form of weak ordering, which provides very few guarantees. Weak ordering
allows almost any operation to be reordered, which enables a variety of
hardware optimizations but is also a nightmare to program at the lowest
levels.
Read more here:
https://homes.cs.washington.edu/~bornholt/post/memory-models.html
Memory Models: x86 is TSO, TSO is Good
Essentially, the conclusion is that x86 in practice implements the old
SPARC TSO memory model.
The big take-away from the talk for me is that it confirms the
observation made may times before that SPARC TSO seems to be the optimal
memory model. It is sufficiently understandable that programmers can
write correct code without having barriers everywhere. It is
sufficiently weak that you can build fast hardware implementation that
can scale to big machines.
Read more here:
https://jakob.engbloms.se/archives/1435
Thank you,
Amine Moulay Ramdane.
Chris M. Thomasson
Feb 1, 2019, 5:42:35 PM2/1/19
to
On 2/1/2019 2:03 PM, Horizon68 wrote:
> Hello,
>
> Read this:
>
>
> About my scalable algorithms..
>
> My scalable algorithms that i have invented are working now on x86.
>
> But i will port them smartly soon to other CPU architecture like ARM..
>
> I think i will port just my scalable MLock and my scalable AMLock for
> Delphi and Freepascal so that my scalable algorithms work on ARM CPU
> architecture, ARM that is of a weak memory model, here is the Memory
> ordering of ARM:
>
> https://en.wikipedia.org/wiki/Memory_ordering
>
>
> Here is my scalable MLock and my scalable AMLock that i have invented:
>
> https://sites.google.com/site/scalable68/scalable-mlock
[...]
> Hello,
>
> Read this:
>
>
> About my scalable algorithms..
>
> My scalable algorithms that i have invented are working now on x86.
>
> But i will port them smartly soon to other CPU architecture like ARM..
>
> I think i will port just my scalable MLock and my scalable AMLock for
> Delphi and Freepascal so that my scalable algorithms work on ARM CPU
> architecture, ARM that is of a weak memory model, here is the Memory
> ordering of ARM:
>
> https://en.wikipedia.org/wiki/Memory_ordering
>
>
> Here is my scalable MLock and my scalable AMLock that i have invented:
>
> https://sites.google.com/site/scalable68/scalable-mlock
Do you happen to have a link to the paper where the original MLock is? I
used to have it, but manged to loose it: damn it! I remember coding it
up over in comp.arch some years ago.
Bonita Montero
Feb 3, 2019, 12:39:51 PM2/3/19
to
Can you manic-disordered idiot keep away from this group?
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