EMMS vs FEMMS
Debs
I'm trying to understand the difference between EMMS and FEMMS, and
can't find references to clear up a little confusion that I have.
In the Intel docs (24547204.pdf), it says (about EMMS):
When the EMMS instruction is executed, each tag field in the
x87 FPU tag word is set to 11B (empty).
Each time an MMX instruction is executed, the TOS value is set
to 000B.
Execution of MMX instructions does not affect the other bits in
the x87 FPU status word (bits 0 through 10 and bits 14 and 15) or
the contents of the other x87 FPU registers that comprise the
x87 FPU state (the x87 FPU control word, instruction pointer,
data pointer, or opcode registers).
So, it looks like EMMS clears the TOS pointer in the FPU status
register and (as does every MMX instruction) it sets the FPU tag word
to all 1s.
In the AMD docs (21928.pdf), it says (about FEMMS):
Like the EMMS instruction, the FEMMS instruction can be used
to clear the MMX state following the execution of a block of
MMX instructions. Because the MMX registers and tag words are
shared with the floating-point unit, it is necessary to clear
the state before executing floating-point instructions.
Unlike the EMMS instruction, the contents of the
MMX/floating-point registers are undefined after a FEMMS
instruction is executed. Therefore, the FEMMS instruction
offers a faster context switch at the end of an MMX routine
where the values in the MMX registers are no longer required.
elsewhere, it says:
Every time the processor executes a 3DNow! or MMX instruction,
all the floating-point register tag bits are set to zero
(00b=valid), except for the FEMMS and EMMS instructions,
which set all tag bits to one (11b=empty).
In the Athlon Optimisation (22007.pdf) manual it says:
To free up all remaining occupied FPU stack register and set
the x87 stack pointer to zero, use the FEMMS or EMMS
So, this also looks like it sets the FPU tag register to all 1s, and
clears the TOS.
I can't see a difference between the operation of the two
instructions, but AMD say that FEMMS leave the FPU registers in an
undefined state and that EMMS leaves them in a defined state. Can
anyone help clarify this for me?
--
Debs
de...@dwiles.nospam.demon.co.uk
----
If it's true that we are here to help others, then what exactly are the others here for?
Norbert Juffa
"Debs" <de...@spamfree.net> wrote in message
news:2euq7ugbal2l0o3do...@4ax.com...
> Hi all...
>
> I'm trying to understand the difference between EMMS and FEMMS, and
> can't find references to clear up a little confusion that I have.
[many quotes from documentation deleted ...]
> I can't see a difference between the operation of the two
> instructions, but AMD say that FEMMS leave the FPU registers in an
> undefined state and that EMMS leaves them in a defined state. Can
> anyone help clarify this for me?
All the qouted documentation correctly describes the behavior, best I can
tell.
On Athlon, there is actually no difference, i.e. FEMMS == EMMS. But given
how FEMMS is defined, don't rely on this as AMD could change it as they
see fit.
On K6 family CPUs, the actual register contents is undefined after FEMMS.
The register contents is observable via FSAVE, regardless of whether the tag
word marks the registers "invalid" or not. FEMMS saves work by not updating
the register contents when the switch occurs. So the status word, control
word,
and tag word all look the same after EMMS or FEMMS, but the data registers
differ. I am not sure about the error pointers in the x87 state.
Since in normal programming practice, nobody relies on the contents of x87
registers marked "invalid", FEMMS is a save substitute for EMMS, but faster.
-- Norbert
Debs
On Thu, 28 Feb 2002 16:56:30 +0000 (UTC), Norbert Juffa spake thus:
>All the qouted documentation correctly describes the behavior, best I can
>tell.
Thanks. It looks like I didn't misunderstand then, its the
documentation that wasn't clear :)
>
>On Athlon, there is actually no difference, i.e. FEMMS == EMMS. But given
>how FEMMS is defined, don't rely on this as AMD could change it as they
>see fit.
That's what I wondered about. I can see that it's the same on the
Athlon, and the descriptions (as quoted) do indicate that they are the
same on all processors that support both instructions. That makes
documenting it easier (no need to try and describe in detail, the main
thing is that I didn't misunderstand it).
>
>On K6 family CPUs, the actual register contents is undefined after FEMMS.
>The register contents is observable via FSAVE, regardless of whether the tag
>word marks the registers "invalid" or not. FEMMS saves work by not updating
>the register contents when the switch occurs. So the status word, control
>word,
>and tag word all look the same after EMMS or FEMMS, but the data registers
>differ. I am not sure about the error pointers in the x87 state.
I can't see how the data registers differ if netiher is specifically
documented as changing them, but as you say I can observe that by
using the FSAVE instruction when I have time to test all the different
instructions I want to look into :)