About mov instruction and gs register Options

leilei

unread,

Apr 30, 2008, 12:55:11 PM4/30/08

to

I am writting a program for target board which have a 486 cpu, 512K
ram(0x0 to 0x7ffff), 512k flash (0x80000 to 0xFFFFF).My program will
be burned into flash.
My program is to initialize the GDT, IDT, TSS, move them to memory.
Now I can enter protected model and mov GDT, IDT correctly.But when I
am about to mov TSS, some exception came out, and the CPU reset
automaticly. The code casue the problem is like this:
mov cx, gdt_idx
mov gs, cx
when cpu run to the instuction 'mov gs, cx', CPU will reset.
i can assure the value in cx is correctly.

Frank Kotler

unread,

Apr 30, 2008, 8:43:59 PM4/30/08

to

Your system appears to have a different opinion. Better show us how you
calculate "gdt_idx".

I wouldn't "expect" the system to reboot until you try to *use* gs. Does
it still reboot if you put "here: jmp here" right after "mov gs, cx"? I
suppose you've tried that... Only thing I can think of...

Best,
Frank

Alexei A. Frounze

unread,

Apr 30, 2008, 11:04:51 PM4/30/08

to

I'm not sure if I should interpret "Now I can enter protected model
and mov GDT, IDT correctly" as a claim that implies that the following
is true:

1. MOV DS/ES/SS, non-NULL selector doesn't cause any exceptions
2. the exceptions are actually caught by the exception handlers

That's because of this statement: "when cpu run to the instuction 'mov

gs, cx', CPU will reset".

Most likely your GDT is incorrect and your exception handlers don't
work either (if they exist at all).

Finally, I have no idea what you mean by "But when I am about to mov
TSS". There's no MOV TSS instruction (only LTR). Did you mean you
relocated the TSS in memory from one place to another?

Alex

Wolfgang Kern

unread,

May 1, 2008, 4:05:03 AM5/1/08

to

"leilei" wrote:

A MOV GS, with whatsoever value wont raise an exception except
if the CPU don't got a GS (EXCeption06 on x286 and previous).
512 KB RAM ? mmh, are you sure you have a 486 CPU ?

__
wolfgang

leilei

unread,

May 1, 2008, 10:55:45 AM5/1/08

to

Hi, I can assure the CPU is 486.
I do not understand the 'EXCeption06 on x286 and previous' you just
mentioned. can you give me more information?

leilei

unread,

May 1, 2008, 10:54:08 AM5/1/08

to

Hi, I calculate the gdt_idx like this:

gdt_idx equ 1 * SIZEOF(DESC) ;DESC is a struct of Segment
Descriptor.
...

mov cx, gdt_idx
mov gs, cx

;CPU can not even run to here after 'mov gs, cx', because it already
restarted.

I tried to change gs to es, but it still not work.

I even use a valide selector which executed successfully before to
replace gdt_idx, the CPU still reboot at this place.

Gil Hamilton

unread,

May 1, 2008, 9:17:08 AM5/1/08

to

"Wolfgang Kern" <spam...@crayne.org> wrote in news:fvc02f$9s$1
@newsreader2.utanet.at:

Not sure where you got this. According to the Intel programming manual:
If the destination operand is a segment register (DS, ES, FS,
GS, or SS), the source operand must be a valid segment selector.
In protected mode, moving a segment selector into a segment
register automatically causes the segment descriptor information
associated with that segment selector to be loaded into the
hidden (shadow) part of the segment register. While loading this
information, the segment selector and segment descriptor
information is validated (see the "Operation" algorithm below).
The segment descriptor data is obtained from the GDT or LDT
entry for the specified segment selector.

GH

Wolfgang Kern

unread,

May 1, 2008, 5:13:59 PM5/1/08

to

"leilei" wrote:

...

>> A MOV GS, with whatsoever value wont raise an exception except
>> if the CPU don't got a GS (EXCeption06 on x286 and previous).
>> 512 KB RAM ? mmh, are you sure you have a 486 CPU ?

> Hi, I can assure the CPU is 486.

> I do not understand the 'EXCeption06 on x286 and previous' you just
> mentioned. can you give me more information?

FS,GS weren't available on 286 and earlier, so these opcodes were
treated as 'illegal' (EXC06).

But anyway my statement is wrong because I assumed a defined GDT ...
so if your GDT is limited to a certain value then any attempt
to load a selector above it will result in EXC0D (GP#13),

and if your selector points to a descriptor which takes further
actions that aren't covered yet, you may see several exceptions
of any kind (stack/task/GP...)

The selector value you have in CX will point to the descriptor
at offset 'CX AND FFF8h' in your GDT if bit2 of CX is zero.

__
wolfgang

Perhaps my short overview is of some use for you:
_________________________________________________________
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Strict//EN"
"http://www.w3.org/TR/html4/strict.dtd">

<title>x86descriptors</title>
<style type="text/css">

</style>
</head>

<u>IA32 Descriptors</caption></u>

<table border="1" frame="box" rules="all" bgcolor="#FFFFFF" height="200"
cellspacing="0" cellpadding="0"

bordercolor="#808080">
<colgroup>
<col width="8">
<col width="24" align="middle" span=8>
<col width="200" align="left" valign="top">
</colgtroup>

<tr> <td>7</td>
<td colspan="8">BASE 31..24</td>
<td rowspan="9">
<pre><b><u>
DATA [93][GDT,LDT]</b></u>
G 4Kb granular limit
B 32-bit stack
P present
E expand down (stack)
W writable
A accessed</pre>
</td>
</tr>

<tr> <td>1</td>
<td rowspan="2" colspan="8">LIMIT 0..15</td> </tr>

<tr style="font-size:7pt;">
<td></td>
<td>7</td>
<td>6</td>
<td>5</td>
<td>4</td>
<td>3</td>
<td>2</td>
<td>1</td>
<td>0</td> </tr>
</table>
<br>
<table border="1" frame="box" rules="all" bgcolor="#FFFFFF" height="200"
cellspacing="0" cellpadding="0"

bordercolor="#808080">

<tr> <td>7</td>
<td colspan="8">BASE 31..24</td>
<td rowspan="9">
<pre><b><u>
CODE [9b][GDT,LDT]</u></b>
G 4Kb granular
B 32-bit
P present
C confirming
R readable
A accessed</pre>
</td></tr>

<tr> <td>5</td>
<td>P</td>
<td colspan="2">DPL</td>
<td colspan="2" style="border-width:medium;border-color:#000000;
border-style:double; padding:0px;"><b>1

1</td>
<td><b>C</td>
<td><b>R</td>
<td><b>A</td> </tr>

<tr> <td>1</td>
<td rowspan="2" colspan="8">LIMIT 0..15</td> </tr>

<table border="1" frame="box" rules="all" bgcolor="#ffffff" height="200"
cellspacing="0" cellpadding="0"

bordercolor="#808080">
<colgroup>
<col width="8">
<col width="24" align="middle" span=8>
<col width="200" align="left" valign="top">
</colgtroup>

<tr> <td>7</td>
<td colspan="8">BASE 31..24</td>
<td rowspan="9"><pre><u><b>
TASK-switch [81/89]</u>
[GDT]</b>
G 4Kb granular limit
P present
BT 32-bit
BS task is busy</pre> </td></tr>

</tr>

<tr> <td>1</td>
<td rowspan="2" colspan="8">LIMIT 0..15</td> </tr>

<br>
<table border="1" frame="box" rules="all" bgcolor="#ffffff" height="200"
cellspacing="0" cellpadding="0"

bordercolor="#808080">
<colgroup>
<col width="8">
<col width="24" align="middle" span=8>
<col width="200" align="left" valign="top">
</colgtroup>

<tr> <td>7</td>
<td rowspan="2" colspan="8">Linear Address 31..16</td>
<td rowspan="9"><pre><u><b>
LDT [82][GDT]</b></u></td></tr>

<tr> <td>4</td>
<td colspan="8">reserved</td> </tr>
<tr> <td>3</td>
<td colspan="8">SEGMENT-</td> </tr>
<tr> <td>2</td>
<td colspan="5">SELECTOR</td>
<td>x</td>
<td colspan="2">RPL</td> </tr>
<tr> <td>1</td>
<td rowspan="2" colspan="8">Linear Address 15..0</td> </tr>

<br>
<table border="1" frame="box" rules="all" bgcolor="#ffffff" height="200"
cellspacing="0" cellpadding="0"

bordercolor="#808080">
<colgroup>
<col width="8">
<col width="24" align="middle" span=8>
<col width="200" align="left" valign="top">
</colgtroup>

<tr> <td>7</td>
<td rowspan="2" colspan="8">Offset 31..16</td>
<td rowspan="9"><pre><u><b>
Call-GATE [84/8c]
[GDT,LDT]</b></u>
T 32-bit
L LDT (else GDT)
Dwords copied from
callers stack.
</td></tr>
<tr> <td>6</td> </tr>

<tr> <td>4</td>
<td colspan="4">0 0 0 0</td>
<td colspan="4">Dwords </td>
</tr>
<tr> <td>3</td>
<td colspan="8">SEGMENT-</td> </tr>
<tr> <td>2</td>
<td colspan="5">SELECTOR</td>
<td>L</td>
<td colspan="2">RPL</td> </tr>
<tr> <td>1</td>
<td rowspan="2" colspan="8">Offset 15..0</td> </tr>

<table border="1" frame="box" rules="all" bgcolor="#ffffff" height="200"
cellspacing="0" cellpadding="0"

bordercolor="#808080">
<colgroup>
<col width="8">
<col width="24" align="middle" span=8>
<col width="200" align="left" valign="top">
</colgtroup>

<tr> <td>7</td>
<td rowspan="2" colspan="8">reserved</td>
<td rowspan="9"><pre><u><b>
TASK-GATE [85/8d]
[GDT,IDT,LDT]</b></u>
T: 32-bit
</td></tr>
<tr> <td>6</td> </tr>
<tr> <td>5</td>
<td>P</td>
<td colspan="2">DPL</td>
<td style="border-color:#000000;border-width:medium;border-style:double">
<b>0</td>
<td><b>T</td>
<td colspan= "3"
style="border-color:#000000;border-width:medium;border-style:double">
<b>1 0 1</td>
</tr>

<tr> <td>4</td>
<td colspan="8">reserved</td> </tr>
<tr> <td>3</td>
<td colspan="8">SEGMENT-</td> </tr>
<tr> <td>2</td>
<td colspan="5">SELECTOR</td>
<td>x</td>
<td colspan="2">RPL</td> </tr>
<tr> <td>1</td>
<td rowspan="2" colspan="8">reserved</td> </tr>

<table border="1" frame="box" rules="all" bgcolor="#ffffff" height="200"
cellspacing="0" cellpadding="0"

bordercolor="#808080">
<colgroup>
<col width="8">
<col width="24" align="middle" span=8>
<col width="200" align="left" valign="top">
</colgtroup>

<tr> <td>7</td>
<td rowspan="2" colspan="8">Offset 31..16</td>
<td rowspan="9"><pre><u><b>
INT-GATE [86/8e][IDT]</b></u>
T 32-bit
disables IRQ,
TRAP and NT cleared
until IRET
</td></tr>
<tr> <td>6</td> </tr>
<tr> <td>5</td>
<td>P</td>
<td colspan="2">DPL</td>
<td style="border-color:#000000;border-width:medium;border-style:double">
<b>0</td>
<td><b>T</td>
<td colspan= "3"
style="border-color:#000000;border-width:medium;border-style:double">
<b>1 1 0</td>
</tr>

<tr> <td>4</td>
<td colspan="8">reserved</td> </tr>
<tr> <td>3</td>
<td colspan="8">SEGMENT-</td> </tr>
<tr> <td>2</td>
<td colspan="5">SELECTOR</td>
<td>x</td>
<td colspan="2">RPL</td> </tr>
<tr> <td>1</td>
<td rowspan="2" colspan="8">Offset 15..0</td> </tr>

<table border="1" frame="box" rules="all" bgcolor="#ffffff" height="200"
cellspacing="0" cellpadding="0"

bordercolor="#808080">
<colgroup>
<col width="8">
<col width="24" align="middle" span=8>
<col width="200" align="left" valign="top">
</colgtroup>

<tr> <td>7</td>
<td rowspan="2" colspan="8">Offset 31..16</td>
<td rowspan="9"><pre><u><b>
INT-TRAP [87/8f][IDT]</b></u>
T 32-bit
IRQ-status unchanged,
TRAP and NT cleared
until IRET
</td></tr>
<tr> <td>6</td> </tr>
<tr> <td>5</td>
<td>P</td>
<td colspan="2">DPL</td>
<td style="border-color:#000000;border-width:medium;border-style:double">
<b>0</td>
<td><b>T</td>
<td colspan= "3"
style="border-color:#000000;border-width:medium;border-style:double">
<b>1 1 1</td>
</tr>

<tr> <td>4</td>
<td colspan="8">reserved</td> </tr>
<tr> <td>3</td>
<td colspan="8">SEGMENT-</td> </tr>
<tr> <td>2</td>
<td colspan="5">SELECTOR</td>
<td>x</td>
<td colspan="2">RPL</td> </tr>
<tr> <td>1</td>
<td rowspan="2" colspan="8">Offset 15..0</td> </tr>

</font>
</body>
</html>

Wolfgang Kern

unread,

May 1, 2008, 4:27:21 PM5/1/08

to

Gil Hamilton mentioned:
...

>>> when cpu run to the instuction 'mov gs, cx', CPU will reset.
>>> i can assure the value in cx is correctly.

>> A MOV GS, with whatsoever value wont raise an exception except
>> if the CPU don't got a GS (EXCeption06 on x286 and previous).
>> 512 KB RAM ? mmh, are you sure you have a 486 CPU ?

> Not sure where you got this. According to the Intel programming manual:
> If the destination operand is a segment register (DS, ES, FS,
> GS, or SS), the source operand must be a valid segment selector.
> In protected mode, moving a segment selector into a segment
> register automatically causes the segment descriptor information
> associated with that segment selector to be loaded into the
> hidden (shadow) part of the segment register. While loading this
> information, the segment selector and segment descriptor
> information is validated (see the "Operation" algorithm below).
> The segment descriptor data is obtained from the GDT or LDT
> entry for the specified segment selector.

You are right, I assumed a fully defined GDT/LDT setup ...
It will raise exception0D for a value beyond GDT-limit
or a not present LDT.

__
wolfgang