SweetAda on NEORV32

[Gabriele Galeotti]

Hi all.

I’ve created a NEORV32 target platform in SweetAda (https://github.com/gabriele-galeotti).

NEORV32 (https://github.com/stnolting/neorv32) is a popular RISC-V SoC implementation in VHDL, suited for FPGAs.

The setup so far is blatantly primitive and runs under simulation by means of GHDL, outputting a welcome message inside the simulated UART console and continuously output the value of the mtime timer.

So far I have no FPGA hardware (besides the time) ready to create a real implementation, so if someone is using NEORV32 on real hardware, and is willing to test, it will be very interesting to know about a OK/KO flag feedback. The current setup needs only UART clocking parameters in the CTRL register, which I suppose it depends on the actual clock configuration. In the meantime I will continue to develop things inside the simulated GHDL environment.

Best regards,
G