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MII SFD Detection with FPGA Logic
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bln...@googlemail.com
Dec 13, 2012, 9:34:19 AM12/13/12
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Hello,
I have to detect the Start of a Ethernet Frame. So I want to make use of a FPGA. The FPGA will be connected to the MII pins of the PHY (TXD 0-3 and RXD 0-3, the Clocks, TX_EN and RX_DV). What I know from the IEEE802.3 Datasheets is that the preamble will be send as 14 Nibbles and after that 2 Nibbles the SFD.
In transmitting case it will be like that:
TxD0 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data
TxD1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data
TxD2 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data
TxD3 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Data
TxEn 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1..
So I thought that I can trigger the rising edge from TxD3 in the 16. Cylce or from Tx_En. But if I only check one wire there could be errors right? How do I check for more than one Cylce? Do I need a State machine? Is this the correct path?
I found the example of SFD detection from OpenCores.org of the EtherMac project, but i dont have any verilog or vhdl knowledge.
Thatswhy i wanted to use the Xilinx ISE Schematic tool and some fast logic.
So can you help me by giving me some advice how to make use of some fast logic.
Do i need some FIFOs oder Latches?
Thank you very much and greetings
I have to detect the Start of a Ethernet Frame. So I want to make use of a FPGA. The FPGA will be connected to the MII pins of the PHY (TXD 0-3 and RXD 0-3, the Clocks, TX_EN and RX_DV). What I know from the IEEE802.3 Datasheets is that the preamble will be send as 14 Nibbles and after that 2 Nibbles the SFD.
In transmitting case it will be like that:
TxD0 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data
TxD1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data
TxD2 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data
TxD3 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Data
TxEn 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1..
So I thought that I can trigger the rising edge from TxD3 in the 16. Cylce or from Tx_En. But if I only check one wire there could be errors right? How do I check for more than one Cylce? Do I need a State machine? Is this the correct path?
I found the example of SFD detection from OpenCores.org of the EtherMac project, but i dont have any verilog or vhdl knowledge.
Thatswhy i wanted to use the Xilinx ISE Schematic tool and some fast logic.
So can you help me by giving me some advice how to make use of some fast logic.
Do i need some FIFOs oder Latches?
Thank you very much and greetings
herrman...@gmail.com
Jul 17, 2016, 5:58:51 PM7/17/16
to
On Thursday, December 13, 2012 at 6:34:19 AM UTC-8, bln...@googlemail.com wrote:
(snip)
> I found the example of SFD detection from OpenCores.org of the EtherMac project,
> but i dont have any verilog or vhdl knowledge.
If you can understand digital logic, how it is wired together, for example in
thinking about how to wire together 7400 series ICs, you will have an easy time
learning either Verilog or VHDL.
Think in terms of wires and gates, write in either HDL.
> Thatswhy i wanted to use the Xilinx ISE Schematic tool and some fast logic.
> So can you help me by giving me some advice how to make use of some fast logic.
> Do i need some FIFOs oder Latches?
Once you know one of Verilog and VHDL, you will almost be able to read the other.
Then learn just a little about the other, and you can easily read it, too.
-- glen
(snip)
> I found the example of SFD detection from OpenCores.org of the EtherMac project,
> but i dont have any verilog or vhdl knowledge.
thinking about how to wire together 7400 series ICs, you will have an easy time
learning either Verilog or VHDL.
Think in terms of wires and gates, write in either HDL.
> Thatswhy i wanted to use the Xilinx ISE Schematic tool and some fast logic.
> So can you help me by giving me some advice how to make use of some fast logic.
> Do i need some FIFOs oder Latches?
Then learn just a little about the other, and you can easily read it, too.
-- glen
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