could anyone give me an example in CRC in both Hardware(using shift
registres and x-or's) and Software(polynomial & checksum)
implementation to distinguish between them?!!
thanks alot.
A standard software CRC, (as I describes in (1)), uses the first
function (icrc1) to create a table of the CRC of 256 characters. It
then uses this table to calculate the CRC of an array of characters
passed to icrc. This relies heavily on looking into arrays - a task
easy to do in software, but not efficient in hardware.
For hardware CRC, bit operations can be executed in parallel. Thus, a
hardware CRC consist of numerous bit-wise exclusive OR operations. (2)
Illustrate hardware CRC in VHDL (note that the results from both
algorithms are the same).
Software CRC algorithm (1):
----------------------------------------
unsigned short icrc1(unsigned short crc, unsigned char onech)
{
int i; unsigned short ans=(crc ^ onech << 8);
for (i=0;i<8;i++) {
if (ans & 0x8000) {ans = (ans <<= 1) ^ 4129;}
else {ans <<= 1;}
}
return ans;
}
typedef unsigned char uchar;
#define LOBYTE(x) ((uchar)((x) & 0xFF))
#define HIBYTE(x) ((uchar)((x) >> 8))
unsigned short icrc(unsigned short crc, unsigned char *bufptr, unsigned
long len, short jinit, int jrev)
{
unsigned short icrc1(unsigned short crc, unsigned char onech);
static unsigned short icrctb[256],init=0;
static uchar rchr[256];
unsigned short j,cword=crc;
static uchar it[16]={0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15};
if (!init) {
init=1;
for (j=0;j<=255;j++) {
icrctb[j]=icrc1(j << 8,(uchar)0);
rchr[j]=(uchar)(it[j & 0xF] << 4 | it[j >> 4]);
}
}
if (jinit >= 0) cword=((uchar) jinit) | (((uchar) jinit) << 8);
else if (jrev < 0)
cword=rchr[HIBYTE(cword)] |rchr[LOBYTE(cword)] << 8;
for (j=1;j<=len;j++)
cword=icrctb[(jrev < 0 ? rchr[bufptr[j]] :
bufptr[j]) ^ HIBYTE(cword)] ^ LOBYTE(cword) <<8;
return (jrev >= 0 ? cword : rchr[HIBYTE(cword)] | rchr[LOBYTE(cword)]
<< 8);
}
Hardware CRC algorithm (2):
-----------------------------------------
package body PCK_CRC16_D8 is
-- polynomial: (0 5 12 16) data width: 8
-- convention: the first serial data bit is D(7)
function nextCRC16_D8 ( Data: std_logic_vector(7 downto0);
CRC: std_logic_vector(15 downto0) )
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(15 downto 0);
variable NewCRC: std_logic_vector(15 downto 0);
begin
D := Data; C := CRC;
NewCRC(0) := D(4) xor D(0) xor C(8) xor C(12);
NewCRC(1) := D(5) xor D(1) xor C(9) xor C(13);
NewCRC(2) := D(6) xor D(2) xor C(10) xor C(14);
NewCRC(3) := D(7) xor D(3) xor C(11) xor C(15);
NewCRC(4) := D(4) xor C(12);
NewCRC(5) := D(5) xor D(4) xor D(0) xor C(8) xor C(12) xor C(13);
NewCRC(6) := D(6) xor D(5) xor D(1) xor C(9) xor C(13) xor C(14);
NewCRC(7) := D(7) xor D(6) xor D(2) xor C(10) xor C(14) xor C(15);
NewCRC(8) := D(7) xor D(3) xor C(0) xor C(11) xor C(15);
NewCRC(9) := D(4) xor C(1) xor C(12);
NewCRC(10) := D(5) xor C(2) xor C(13);
NewCRC(11) := D(6) xor C(3) xor C(14);
NewCRC(12) := D(7) xor D(4) xor D(0) xor C(4) xor C(8) xor C(12) xor
C(15);
NewCRC(13) := D(5) xor D(1) xor C(5) xor C(9) xor C(13);
NewCRC(14) := D(6) xor D(2) xor C(6) xor C(10) xor C(14);
NewCRC(15) := D(7) xor D(3) xor C(7) xor C(11) xor C(15);
return NewCRC;
end nextCRC16_D8;
end PCK_CRC16_D8;
- Nir
Mahesh Naik
Mahesh thanks alot , I will read about Roos compression
:)
Thanks Guys