I am working on a project, where we are trying to make a development
environment for new ASIP processor design. This project, among other
parts, contains compiler and simulator generator. For these two
parts, I would need some C compiler, that supports arbitrary bit-width
integers.
For the simulator, we need to generate code that simulates registers
of arbitrary bit width and for compiler generator, we would need to
optimize C code that describes instruction's behavior to extract
instruction selectrion rule for each instruction,
Have you heard or read about such compiler? (any references would be
useful)
P.S.: So far, I have found Valen-C project (quite old, not made it
work yet), then I tried the clang frontend (it seems that to implement
support would be quite problematic but not impossible) and also I am
going to try some synthetizers that generate HW from C code.
Have you already been looking at CoWare Processor Designer[1], it may
give you a flexible compiler construction toolkit, simulator generator
and C-to-HDL design flow for your ASIP. As it seems that you're a
student or working for a University you may be able to purchase a
license at a very reasonable price via EuroPractice[2].
Cheers,
Bjoern
[1] http://www.coware.com/products/processordesigner.php
[2] http://www.europractice.com/
LLVM supports "really big integers of arbitrary length" but places size
restrictions on values being returned from funtions (looks like twice the
size of a register)
I don't know how much of that is exposed through its C frontend, but it
might at least be worth a look.
> Have you already been looking at CoWare Processor Designer[1], it may
> give you a flexible compiler construction toolkit, simulator generator
> and C-to-HDL design flow for your ASIP. As it seems that you're a
> student or working for a University you may be able to purchase a
> license at a very reasonable price via EuroPractice[2].
Or use the language behind the CoWare tools, SystemC, which has a free
and open source reference implementation (www.systemc.org). It's a
template library for C++ aimed at hardware modeling. Standardized as
IEEE 1666, which unusually for the IEEE can be downloaded free.
Be warned the reference implementation has terrible performance for
anything over 64-bits wide. The discrete event simulation kernel also
can be a significant overhead, but that's the price you pay for
convenient functionality.
Unfortunately this reference implementation is the basis of all the
commercial tools as well, and I do not know of any high performance
implementation (there are many claims, but none independently
verified).
CoWare's tools are good, and they have other tools aimed at ASICs in
general. There are plenty of others out there as well. Generally they
add a graphical development environment (Eclipse based in many cases,
including CoWare) and libraries of pre-packaged IP models (bus
protocols, common peripherals, transactors). However the underlying
functionality of SystemC may be sufficient for your purposes.
HTH,
Jeremy
> Or use the language behind the CoWare tools, SystemC, which has a
> free and open source reference implementation
> (www.systemc.org). It's a template library for C++ aimed at hardware
> modeling. Standardized as IEEE 1666, which unusually for the IEEE
> can be downloaded free.
As far as I know the language behind CoWare's Processor Designer is LISA
. On Coware's website it says:
"The key to Processor Designer's automation is its Language for
Instruction Set Architectures, LISA 2.0. In contrast to SystemC, which
has been developed for efficient specification of systems, LISA 2.0 is
a processor description language that incorporates all necessary
processor-specific components such as register files, pipelines, pins,
memory and caches, and instructions. "
> CoWare's tools are good, and they have other tools aimed at ASICs in
> general. There are plenty of others out there as well. Generally
> they add a graphical development environment (Eclipse based in many
> cases, including CoWare) and libraries of pre-packaged IP models
> (bus protocols, common peripherals, transactors). However the
> underlying functionality of SystemC may be sufficient for your
> purposes.
I'm not quite sure how SystemC might help the original poster in
constructing the compiler targeting arbitrary bit-width integers.
Cheers,
Bjoern
> Jeremy Bennett wrote:
>
>> Or use the language behind the CoWare tools, SystemC, which has a free
>> and open source reference implementation (www.systemc.org). It's a
>> template library for C++ aimed at hardware modeling. Standardized as
>> IEEE 1666, which unusually for the IEEE can be downloaded free.
>
> As far as I know the language behind CoWare's Processor Designer is LISA
> . On Coware's website it says:
>
> "The key to Processor Designer's automation is its Language for
> Instruction Set Architectures, LISA 2.0. In contrast to SystemC, which
> has been developed for efficient specification of systems, LISA 2.0 is a
> processor description language that incorporates all necessary
> processor-specific components such as register files, pipelines, pins,
> memory and caches, and instructions. "
That is true. LISA is used to specify the processor, so this will be
simpler if the OP can obtain the tools and the LISA design philosophy is
suitable for the project. I believe the CoWare tools are now all
integrated, and the simulation models generated will be in SystemC.
> I'm not quite sure how SystemC might help the original poster in
> constructing the compiler targeting arbitrary bit-width integers.
I'd focussed on the simulator part of the question. However, since
SystemC provides a set of types of arbitrary width it will be of general
use in this field.
The OP might like to look at Target Compiler Technologies
(www.retarget.com), who have tools to design ASIPs and generate the
compiler tool chain automatically.
HTH,
Jeremy