how to synthesis a circuit by using only type gate--nand2
Guang-Wan Liao
I want to synthesis a circuit by using only one type gate--nand2.
I use Synopsys Design Compiler and I disable the others of my cell library.
When I synthesis some circuit, Synopsys Design Compiler always say no
inverter in my cell library.
Many thanks in advance
Guang-Wan
Guang-Wan Liao
Muzaffer Kal
Sounds like you're trying to get DC to do your homework for you. I
still have a solution for you as it will get you to do some scripting
which is another skill you need. Why don't you add a single inverter
to your list of acceptable cells and when synthesis finishes, search
and replace all the inverters with nand2s which I hope you know how to
do.
Muzaffer Kal
http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations
John Myers
I'm trying to translate a gate level netlist from one technology
to a different technology. At first, I was getting the following error:
>>> Error: The target library does not contain an AND, OR, or NOR.
I determined that the "target_library" had a "dont_use" attribute
on all of the cells, so I removed this attribute, and reran translate.
Now I'm getting the same error that Guang-Wan is seeing:
>>> Error: The target library does not contain an inverter.
>>> An inverter is required for mapping. (OPT-101)
Well, the library does contain an inverter. What is going on here?
I even tried translating to gtech (which worked) and then compiling
to my target_library, and it gave the same error... Obviously, I am
missing something fundamental here? I'm at a loss...
Any assistance would be greatly apprreciated...
John Myers
Muzaffer Kal wrote:
--
john myers
Displays Group Engineer
National Semiconductor
817-468-6680
Muzaffer Kal
<bjx...@mail-te.nsc.com> wrote:
>I have a follow up question here...
>
>I'm trying to translate a gate level netlist from one technology
>to a different technology. At first, I was getting the following error:
>
>>>> Error: The target library does not contain an AND, OR, or NOR.
>
>I determined that the "target_library" had a "dont_use" attribute
>on all of the cells, so I removed this attribute, and reran translate.
>Now I'm getting the same error that Guang-Wan is seeing:
>
>>>> Error: The target library does not contain an inverter.
>>>> An inverter is required for mapping. (OPT-101)
>
>Well, the library does contain an inverter. What is going on here?
>I even tried translating to gtech (which worked) and then compiling
>to my target_library, and it gave the same error... Obviously, I am
>missing something fundamental here? I'm at a loss...
>
>Any assistance would be greatly apprreciated...
>
>John Myers
Is it possible that you have a collusion between the gate names of
your input gate level netlist and your target_library ? I guess you
have also a definition for each type of cell in the input gate level
netlist which could be conflicting with the target library
definitions.
Also can you synthesize an RTL module with your target library setup?
Maybe your problem is not related to technology mapping.
Finally try doing a report_lib on your target library and see what
cells DC thinks it has.
John Myers
I am able to synthesize from RTL into the target library. I'm
thinking that there is some attribute of some sort associated
with the library that is not being set properly, but I am not
familiar enough with how are libraries are generated to
know what to look for...
The fact that the library cells all have a "dont_use" attribute
set seems a little fishy to me, but again, I don't know if this
is a normal thing to do when a library is generated...
thanks though for your suggestions...
john myers
Muzaffer Kal wrote:
--