CFP (2): International Workshop on Logic Synthesis
Luciano Lavagno
International Workshop on Logic Synthesis
Granlibakken Resort, Lake Tahoe, California
June 27-30, 1999
Call for Papers
Logic Synthesis has traditionally been focused on optimization
techniques
for combinational and sequential circuits through the manipulation of
Boolean equations and state machines. IWLS '99, the eighth workshop in
this
series, seeks papers both on these topics and on new directions in
synthesis-based design methodology. Topics of interest include (but are
not
limited to):
Area, timing, power optimization Logic synthesis systems
CMOS, ECL, GaAs optimization Designer experiences with
synthesis
Interface specification and synthesis Digital noise and EMI avoidance
Two-Level logic optimization Interaction with physical
design
Multi-Level logic optimization Incremental synthesis and ECO
FSM optimization and encoding Asynchronous logic synthesis
Sequential circuit optimization Reachability and coverage
analysis
Formal verification Retiming and resynthesis
Optimization at the RTL level Technology mapping
Timing verification FPGA and PLD synthesis
Testing and synthesis for test Don't-cares and Boolean
Relations
Interaction with module generators Symbolic Synthesis
Use of synthesis in new applications SAT Algorithms and applications
Reconfigurable computing
The traditional goal of IWLS has been to foster presentation of new
ideas
and work in early stages of development. For this reason, the program is
very open, with high acceptance rate, heavy use of posters and short
talks
for presentation, and large amounts of time in the schedule for
discussions
around posters. Focus group discussions are also used to encourage
exchange
of ideas among all the participants on "hot", new and controversial
topics.
Authors may submit extended abstracts for their proposed presentation.
These
must be no less than 1000 words and no greater than 2500 words (4
pages).
These abstracts are not intended to be complete papers, but rather
should
contain the idea of the proposed presentation. We encourage submissions
in
the early stages of research which may highlight important new problems
without necessarily providing complete solutions. The abstracts should
be
submitted by e-mailing self-contained Postscript, PDF or HTML files
(regular
mail submissions are not accepted) to:
by March 15, 1999. Acceptance notices will be sent by April 1, 1999. A
set
of workshop notes will be distributed to the participants. There will be
no
published proceedings. Authors can request their contribution not to be
included in the notes.
IWLS '99 WEB site: http://www.diegm.uniud.it/iwls99
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General chair:
Fabio Somenzi, University of Boulder, (303) 4430254
fa...@duke.colorado.edu
Program chair:
Luciano Lavagno, Universita' di Udine, +39 0432558288
lav...@diegm.uniud.it
Technical Program Committee
Pranav Ashar NEC C&C Labs Yusuke Matsunaga Fujitsu Labs
Luca Benini U. di Bologna Shin-Ichi Minato NTT
Michel Berkelaar TU-Eindhoven Jose Monteiro U. Tecnica de
Lisboa
Robert Brayton U.C. Berkeley Steven Nowick Columbia
University
Franc Brglez North Carolina S.U. Massoud Pedram U. Southern Cal.
Jordi Cortadella U. Pol. de Catalunya Tsutomu Sasao Kyushu Inst. of
Tech.
Masahiro Fujita Fujitsu Labs Hamid Savoj Magma Design
Automation
Wolfgang Kunz U. of Frankfurt Ellen Sentovich Cadence Berkeley
Labs
Luciano Lavagno U. di Udine Narendra Shenoy Synopsys
Sharad Malik Princeton U. Fabio Somenzi U. of Colorado
Diana Marculescu U. of Maryland Leon Stok IBM Watson Res.
Center
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