Connect 1'b1 to tie high cell in synthesis

[Norman Yang]

Hello all:
I am using the synopsys synthesis tool, dc_shell. There is one thing
that I want to do is dont let the 1'b1 or 1'b0 format left in the
output verilog netlist file. There are some many of left in the
netlist and I dont want to change it manually.

I prefer to let the tool to connect those nets to tie high or tie low
cell, but I did not find out how to do this in dc_shell. Did anyone
here know how to do it. Thank you very much.

Regards!
Norman

[Stefan Kuhnert]

> I prefer to let the tool to connect those nets to tie high or tie low
> cell, but I did not find out how to do this in dc_shell. Did anyone
> here know how to do it. Thank you very much.

The code below is for dc_shell -tcl_mode. Modify the <..> statements.

UNTESTED:

### Creates a TCL list out of a Synopys Collection
proc my_c2l { collection } {
set l [list]

foreach_in_collection e $collection {
lappend l [get_object_name $e]
}

return $l
}

foreach_in_collection design [get_designs *] {
current_design $design

set logic0_cells [my_c2l [get_cells -filter "ref_name == **logic_0**" *]]
set logic1_cells [my_c2l [get_cells -filter "ref_name == **logic_1**" *]]

foreach_in_collection cell $logic0_cells {
set logic_net [all_connected "$cell_name/**logic_0**"]
remove_cell $cell_name
create_cell $cell_name <your_tie0_cell>
connect_net $logic_net $cell_name/<your_tie0_cell/pin_name>
}

### Here comes the same for tie1 cells (a procedure would be better)
}

Cheers,
Stefan

[Nick Jungels]

Most libraries have a tie cell with a dont_use attribute on it. You
can simply remove the dont_use attribute on the tie cell and then
perform a synthesis (or incremental synthesis).

Also make sure that you have issued the set_fix_multiple_port_net
command. This will avoid other assign statements, and fix the assign
statements from a single tie cell that fans out to multiple ports (if
that exists in your design).

It's probably also a good idea to know that inserting tie off cells in
a logically synthesized netlist (as opposed to a physically
synthesized one) isn't a real good idea, depending on the utilization
of your design.

You need to be aware of the routing resources required to hook up tie
cells, congestion in the region, etc. It's also possible to overload
tie cells so be sure you know what the max fanout and max cap values
are for the cell. They may or may not be specifed in the library.

Nick.

stefan....@epost.de (Stefan Kuhnert) wrote in message news:<3f430d2.03051...@posting.google.com>...