gate level verification in verilog using synopsys tools
Kiran
I wrote rtl code for a design and then simulated it in synopsys VCS
when I found it to be ok , I used Design compiler to synthesize the
design using class.db as link and target libraries
after compilation , I saved the design as verilog netlist
now it has various instantiations of various components
when I used the original test bench on this netlist , the tool cribs
that it cannot find
various instance models
can I use the original test bench to simulate this netlist ?
what is the procedure to do this ?
thanks in advance
Kiran
Lars Rzymianowicz
> after compilation , I saved the design as verilog netlist
> now it has various instantiations of various components
> when I used the original test bench on this netlist , the tool cribs
> that it cannot find various instance models
>
> can I use the original test bench to simulate this netlist ?
Yes.
> what is the procedure to do this ?
your netlist now consists of instantiations of lib gates. Now
you need a Verilog file with all those cells described. You should
have received such a file from your lib vendor, besides the .db
file for synthesis...
Lars
--
Address: University of Mannheim; B6, 26; 68159 Mannheim, Germany
Tel: +(49) 621 181-2716, Fax: -2713
email: larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/
Jonas Astrom
"Lars Rzymianowicz" <lar...@ti.uni-mannheim.de> wrote in message
news:3A221B9A...@ti.uni-mannheim.de...
> Kiran wrote:
> > after compilation , I saved the design as verilog netlist
> > now it has various instantiations of various components
> > when I used the original test bench on this netlist , the tool cribs
> > that it cannot find various instance models
> >
> > can I use the original test bench to simulate this netlist ?
>
> Yes.
>
> > what is the procedure to do this ?
>
> your netlist now consists of instantiations of lib gates. Now
> you need a Verilog file with all those cells described. You should
> have received such a file from your lib vendor, besides the .db
> file for synthesis...
Another possibility is to make DC to write library independent code. (If you
are interested in that)
Jonas Astrom
Patrick Schulz
What does that mean? Writing out GEN_TECH cells?
Patrick
--
Patrick Schulz (sch...@rumms.uni-mannheim.de)
University of Mannheim - Dep. of Computer Architecture
68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de
Phone: +49-621-181-2720 Fax: +49-621-181-2713
Jean-Marc Calvez
> Jonas Astrom wrote:
> >
> > "Lars Rzymianowicz" <lar...@ti.uni-mannheim.de> wrote in message
> > news:3A221B9A...@ti.uni-mannheim.de...
> > > Kiran wrote:
(snippage of original text)
> >
> > Another possibility is to make DC to write library independent code. (If you
> > are interested in that)
> >
> > Jonas Astrom
>
> What does that mean? Writing out GEN_TECH cells?
>
> Patrick
Maybe writing out each combinational cell (either gtech or real silicon
library) as its own boolean equation? Sorry, I'm posting from home, so I
don't have my trusty pocket reference guide handy, but its controlled by
a "verilogout_equation" variable or something (just look up all
variables beginning with verilogout, there aren't that many anyway).
To Kiran: I snipped your original post, but I'll give my answer: what
you need (and what you may have, along with the Synopsys db file used in
synthesis) is the verilog description of your library (a huge library
file or a collection of files, one per cell, plus maybe ancillary files
for library-specific UDPs and such). Add this(-ese) file(s) to the
command lines used to invoke your simulator and you should be up and
running in no time.
Well, almost. Before I forgot: since a library is commonly used for
timing simulation (vs zero-delay or unit-delay sim), it is very likely
that the verilog library begins with a `timescale directive; you need to
prepend one to your synopsys-generated netlist. Rather than editing your
netlist (which may be resynthesized several times) you may want to write
the relevant `timescale directive in its own file and use that as the
first argument in the list of verilog files you pass to your simulator.
Regards,
--
Jean-Marc Calvez, jmca...@club-internet.fr
Grenoble, France