Synopsys to Synergy library conversion

[Bob Hoffman]

I'm a Cadence Synergy user and have Synopsys style libraries
to convert. Has anyone gone down a similar route, or heard of
a script to automate the process??

[Christopher Browy]

bo...@oakhill-csic.sps.mot.com writes:

Bob,

I would like to provide some information regarding Synopsys library
conversion for use with Cadence's Synergy synthesis products. I am
Cadence's product marketing manager for Synergy. In addition I would like
to describe library support alternatives used by Synergy customers.

Today, over a dozen ASIC and FPGA vendors support qualified libraries for
Synergy. Initial success has been established for a large number of Synergy
customers who have developed ASICs and FPGAs using these vendor qualified
libraries. Furthermore, Cadence has developed and supports additional
FPGA and ASIC vendor libraries which are typically used for evaluations and
benchmarks. Overall, more than 60 libraries have been used with Synergy.

If certain libraries are not supported for Synergy, Synopsys library
conversion for Synergy can be utilized. Cadence provides library
development services which can leverage existing libraries developed for
other simulation and synthesis tools. Typically the conversion process is
fairly direct relating to library cell models, wire load estimation models,
preferred library cell selection, delay calculation parameters, cost,
timing, and loading parameters. Physical cell information for use with
Cadence's Placement Based Synthesis (PBS) is direct reads from physical
library models supporting Gate Ensemble, Cell3 Ensemble, and Preview.

Cadence's Synergy libraries are developed using the "composite" Verilog
library model format. This format has been in place for several years and
is utilized by ASIC and FPGA vendors to support Cadence's Verilog and VHDL
related products (i.e.. Verilog-XL, Verilog-XL Turbo, Veritime,
Verifault-XL, Synergy, and Leapfrog).

Please contact your local Cadence AE or myself for more information on
this Synopsys conversion process.

Thanks,
Chris Browy

******************************************************
Cadence Design Systems - HDL Design Group
Synergy Marketing Mgr, Verilog Synthesis
270 Billerica Rd.
Chelmsford, Ma 01824
Tel: 508 446 6376
Fax: 508 446 6636
Email: br...@cadence.com
******************************************************

[Hugh Barrass]

Bob Hoffman (bo...@oakhill-csic.sps.mot.com) wrote:
: I'm a Cadence Synergy user and have Synopsys style libraries

: to convert. Has anyone gone down a similar route, or heard of
: a script to automate the process??

:

You have a big problem there! The Synopsys libraries are in a form which
is locked by Synopsys - in order to convert you would need to have the
library manager license & (I believe) the key from whoever produced the
libraries.

You may have noticed that the Synergy libraries are written in verilog -
this can be exploited as it makes it very easy to understand & modify
the libraries (if you use verilog "front-to-back" then you can use the
same libraries for hdl, netlist & synthesis). They use `ifdef for
compiler directives (rather than silly pseudo-comments) & it's
easy to invent new directives & put them in.

If you produced these libraries yourself (or you have control over
the production process) then I would recommed going back to that stage
& reformatting the output. The synopsys format is most unfriendly!
In general, if you hae verilog simulation libraries, with delay
annotation, then you are most of the way there.

It's been a while since I used Synergy (it wasn't called that then),
how is it going nowadays?

Hugh.

<NOT speaking for ACRI - in fact, barely speaking for me...>