why assignment to a single bit of a reg report a error?
lzh
Hi,everyone
This is a simple example module of my question
module test(a,b);
input a;
output [1:0] b;
reg [1:0] b;
always @(a)
begin
assign b[0]=a;
assign b[1]=!a;
end
endmodule
when i use Cadence Verilog-XL to compile it ,Verilog-XL report a
error "Illegal
left-hand-side in assignment",but when i use Veriwell to compile it ,it
does work!
and if i use "assign b={a,!a};"instead of it,the Verilog-XL can compile it
without any error,can anybody explain why?
i really need your help!
thanks!
Jurgen Schulz
you don't use assign in an always block, just try
b[0]=a;
b[1]=!a;
Regards, Jurgen.
Raghu
lzh wrote:
>
> Hi,everyone
> This is a simple example module of my question
> module test(a,b);
> input a;
> output [1:0] b;
> reg [1:0] b;
> always @(a)
> begin
> assign b[0]=a;
> assign b[1]=!a;
> end
> endmodule
>
Hi,
A few related questions:
1. Can you use `assign' statements to
assign values to a `reg' type variable?
I thought you could only `assign' to
nets.
2. Can you combine dataflow (`assign') and
functional (`always') constructs as shown
above?? I thought you could not.
Am I wrong??
Thanks!
--
Raghu ---------------------
ra...@iastate.edu,
(H)(515) 292 1269
---- Grad Student Cpr E ---
m...@silicon-sorcery.com
Raghu <ra...@iastate.edu> writes:
: lzh wrote:
: >
: > Hi,everyone
: > This is a simple example module of my question
: > module test(a,b);
: > input a;
: > output [1:0] b;
: > reg [1:0] b;
: > always @(a)
: > begin
: > assign b[0]=a;
: > assign b[1]=!a;
: > end
: > endmodule
: >
:
: Hi,
:
: A few related questions:
:
: 1. Can you use `assign' statements to
: assign values to a `reg' type variable?
: I thought you could only `assign' to
: nets.
:
: 2. Can you combine dataflow (`assign') and
: functional (`always') constructs as shown
: above?? I thought you could not.
:
Due to a very unfortunate language design choice, there are
two uses of the keyword "assign" in the Verilog language.
One is the familiar continuous assign, which can be used only
at module scope, and can have as its target only an expression of
wires.
The other is the procedural continuous assign, a version of
the force statment, and can be used only in behavorial scopes, and can
have as its target only an expression of registers. This force is in
effect until deassigned (either by using the deassign keyword or by
executing some other procedural continuous assign).
So, the answer to your questions is yes to both; it's just
that the assign isn't the assign you were thinking of...
--
Michael McNamara Silicon Sorcery [37 15.7878' -121 57.4658']
Get my verilog emacs mode (subscribe for free updates!) at
<http://www.silicon-sorcery.com/verilog-mode.html>
Clifford R. Warren
Raghu <ra...@iastate.edu> wrote in article <33475D...@iastate.edu>...
> lzh wrote:
> >
> > Hi,everyone
> > This is a simple example module of my question
> > module test(a,b);
> > input a;
> > output [1:0] b;
> > reg [1:0] b;
> > always @(a)
> > begin
> > assign b[0]=a;
> > assign b[1]=!a;
> > end
> > endmodule
> >
>
> Hi,
>
> A few related questions:
>
> 1. Can you use `assign' statements to
> assign values to a `reg' type variable?
> I thought you could only `assign' to
> nets.
Nope. Sorry you cannot. Continuous assignments can only be
made to "nets", (the "wire" data type).
>
> 2. Can you combine dataflow (`assign') and
> functional (`always') constructs as shown
> above?? I thought you could not.
True, you cannot. A continuous assignment (assign)
cannot be made within a procedural assignment statement
(always).
I like to think of these two type of assignments as:
"continuous" -- assign statements made to wires
and
"procedural" -- assignments made to regs within an always
or an initial statement
By remembering "continuous" and "procedural" this helps me
keep them straight.
David Emrich
lzh wrote:
...
> module test(a,b);
> input a;
> output [1:0] b;
> reg [1:0] b;
> always @(a)
> begin
> assign b[0]=a;
> assign b[1]=!a;
> end
> endmodule
>
> error "Illegal
> left-hand-side in assignment",but when i use Veriwell to compile it ,it
> does work!
> and if i use "assign b={a,!a};"instead of it,the Verilog-XL can compile it
> without any error,can anybody explain why?
Bit select on the left side of a continuous procedural assignment is
prohibited in the OVI 2.0 Verilog LRM.
David Emrich
Exemplar Logic
emr...@exemplar.com
.
