Cadence vs. Synopsys
Vincent Ma
My friend asked me about buying CAD tool. They are considering either
Cadence or Synopsys since both are seems to be popular. Can any body
comment on this. Thanks.
Vincent Ma
jerry english
Which CAD tool?
me...@mench.com
> Which CAD tool?
For what purpose?
Andy Peters
What's your budget?
Vincent Ma
Andy Peters wrote:
The purpose is to do the ASIC design, maybe FPGA first and eventually ASIC
(maybe standard cell). according to my knowledge that he needs VHDL (or
Verilog) simulator, Synthesis, Layout.... But the question is it seems both
Cadence and Synopsys provide similar solution (from schametic, VHDL,
Synthesis, Layout..). So I am puzzled that which one is better (from all
aspects, like performance, learning time, cost, support,...).
Vincent Ma
jerry english
OK, now I can make a comment. For ASIC synthesis I use Ambit's BuildGates. I
like the ability to suck the whole design in (400K gates) and set top level
constraints. Its
fast to produce results. I also like that it came equipped with schematic
viewer, a very
fast timing analyzer and vhdl as well as verilog support. That's if you are
doing large
ASICs. I have ran a design through it using a FPGA library, ugh, the results
were less
than optimal. There might be some switches to set one way or the other to get
better
packing but I really didn't follow up on the issue due to time limitations and
the tool is
sold as an ASIC tool not a FPGA tool.
The support that I have received has been great. I call the apps engineer, he
picks up the
phone and we talk. I have an answer in a few minutes.
Now if you are talking small designs that can fit into FPGAs then move over to
an
ASIC (for whatever reason) you might want to look at Leonardo Spectrum with
the ASIC option. The FPGA part of the tool is very good. I haven't tried the
ASIC
part. You can get an evaluation copy to try out.
Since I do my designs in verilog I use Cadence's Verilog-XL simulator. Its
fast, and its
golden, all ASIC vendors I have looked at consider its results to be correct. I
had no
compatibility issues or problems between BuildGates and the simulator.
I don't do ASIC layouts. I leave that to the ASIC vendor. We do have a FPGA
place and route tool for the Lucent Technology ORCA series FPGAs.
Budget: simulator $25,000
synthesis $90,000
FPGA synthesis $20,000
FPGA layout ?????
Annual maintence on each tool ~10% to 20 % of purchase price
The simulator and synthesis tools run under Unix. The FPGA
tools run under Windows and I think can be purchased to run
under UNIX.
You might want to take a look at www.isdmag.com. They have
articles and tables outlining the tools, prices and features.
I strongly recommend that you get an evaluation copy, try it out
before you purchase. There are some less than perfect tools out there.
Another thing, purchase close to the end of the quarter. The salespeople
are a little more likely to provide discounts. If they don't move on the
price try getting training thrown in for free.
regards
Jerry English
Mike Klein
>
> The purpose is to do the ASIC design, maybe FPGA first and eventually ASIC
> (maybe standard cell). according to my knowledge that he needs VHDL (or
> Verilog) simulator, Synthesis, Layout.... But the question is it seems both
> Cadence and Synopsys provide similar solution (from schametic, VHDL,
> Synthesis, Layout..). So I am puzzled that which one is better (from all
> aspects, like performance, learning time, cost, support,...).
The exact question you're asking keeps entire CAD groups busy for years
:-).
It's not an easy answer and you will need to do a lot of homework
(months or more) to gain a reasonable understanding of the tradeoffs and
how they apply to your specific situation.
BTW, Synopsys and Cadence do not overlap in their tool offerings very
much. Synopsys has no schematic (well, except Viewlogic stuff) and very
limited offerings in the entire layout category. Your comparison is
probably better asked on a tool by tool basis:
layout -- Cadence vs. Avanti
synth -- Cadence vs. Synopsys
simulation -- Cadence vs. Avanti vs. Synopsys vs. a variety of smaller
players
All the above are very expensive tools: $20-30k for a base level
simulator to $400k+ for P&R), with largely UNIX support only (limited NT
in some specific cases).
--
Mike Klein
ATI Research, Inc. (formerly Chromatic Research, Inc.)
kl...@chromatic.com --- to be changing soon
Nigel Elliot
Vincent Ma wrote:
>
> The purpose is to do the ASIC design, maybe FPGA first and eventually ASIC
> (maybe standard cell). according to my knowledge that he needs VHDL (or
> Verilog) simulator, Synthesis, Layout.... But the question is it seems both
> Cadence and Synopsys provide similar solution (from schametic, VHDL,
> Synthesis, Layout..). So I am puzzled that which one is better (from all
> aspects, like performance, learning time, cost, support,...).The exact question you're asking keeps entire CAD groups busy for years
:-).It's not an easy answer and you will need to do a lot of homework
(months or more) to gain a reasonable understanding of the tradeoffs and
how they apply to your specific situation.BTW, Synopsys and Cadence do not overlap in their tool offerings very
much. Synopsys has no schematic (well, except Viewlogic stuff) and very
limited offerings in the entire layout category. Your comparison is
probably better asked on a tool by tool basis:layout -- Cadence vs. Avanti
synth -- Cadence vs. Synopsys
simulation -- Cadence vs. Avanti vs. Synopsys vs. a variety of smaller
players
All the above are very expensive tools: $20-30k for a base level
simulator to $400k+ for P&R), with largely UNIX support only (limited NT
in some specific cases).
--
Mike Klein
ATI Research, Inc. (formerly Chromatic Research, Inc.)
kl...@chromatic.com --- to be changing soon
-- ======================================================================== Nigel Elliot European Product Specialist Mentor Graphics (U.K.) Ltd. Telephone : +44 (0)1635 811462 Rivergate Fax : +44 (0)1635 810110 Newbury Business Park Newbury, Berkshire EMAIL : nigel_...@mentor.com RG14 2QB, England ========================================================================
Loek Frederiks
> Yea - don't forget that small player called Mentor Graphics who only has 50%+
> share of vhdl simulation market with ModelSim. Often seen slugging it out with
> that well known Avanti vhdl simulator ;)
Hmm.... and what's that ? QuickSim ?
Yikes, I hate Cadence Leapfrog:
- mixed level (VHDL and Verilog) is a pain, because Cadence "technology"
consists of two simulators exchanging data with all troubles you can
think of (crashes, failing interprocess communications)
- it has a buggy GUI
- they replaced Cwaves with SimWave, but there's little improvement, in 4.4.2
I can still crash the tools by doing some simple tricks.
Loek.
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Nigel Elliot
> >
> > Yea - don't forget that small player called Mentor Graphics who only has 50%+
> > share of vhdl simulation market with ModelSim. Often seen slugging it out with
> > that well known Avanti vhdl simulator ;)
>
> Hmm.... and what's that ? QuickSim ?
>
I was only joking - as far as I'm aware Avanti doesn't have a vhdl simulator (which
was part of what the original poster was looking for when it was recommended he
look at Avanti).