On Sunday, September 5, 2021 at 7:37:43 AM UTC-5, Quadibloc wrote:
> No, not at all.
>
> One thing, though, should be noted. I think that even the original Cray-I had
> data forwarding - so that if a vector instruction was followed by another vector
> instruction that operated on its result, and which used a different ALU that was
> available, that second instruction started before the first instruction completed
> working on the whole vector.
<
The CRAY-1 had a "chain slot" and if the subsequent instruction was ready to
"go" by the time the chain slot rolled around, the 2 instructions forwarded data
and ran "as one" until the end of the vector arrived.
<
The CRAY-1 X/MP solved this problem and could forward on/at any cycle after
the data arrived. This machine also had 3 AGEN ports to memory per cycle.
>
> So conventional vector operations don't have to have the flaw that VVM
> addresses.
>
> In fact, in my original Concertina architecture, I believe I stole that idea. If you
> look at that architecture, though, you might not see it. It has long vectors
> and short vectors. Long vectors are conventional Cray-I style, and short
> vectors are conventional MMX/SSE/AVX style. Neither one is anything like
> VVM.
>
> So where did I steal VVM?
>
> Elsewhere, I have what I refer to as "dataflow instructions". *This* is
> where I conceptualized something like VVM as belonging. That's where I
> define a series of operations that work on one operand at a time, but are
> chained together, with input arrays and output arrays defined for it.
<
You don't need to consider VVM as "dataflow" instructions, you can just
as easily consider this simply a means to perform several iterations of
a loop simultaneously.