Architecture description languages?

[JimBrakefield]

Ran across LISA 2.0, ArchC and Synopsys nML.
Are any of these (or others) any good?
E.g. being somewhat lazy, can I get a rough and ready RTL generated
without spending a fortune?

Jim Brakefield

[EricP]

Synopsys says nML is apparently called a "processor description language".
I'd not heard of this before but a quick search gets some hits.

There is also Architecture Description Language
https://en.wikipedia.org/wiki/Architecture_description_language

There are "high level synthesis" languages most of which
take C/C++ and generate Verilog or VHDL.
https://en.wikipedia.org/wiki/High-level_synthesis

A Survey and Evaluation of FPGA High-Level Synthesis Tools, 2015
http://ce-publications.et.tudelft.nl/publications/1524_a_survey_and_evaluation_of_fpga_highlevel_synthesis_tools.pdf

And I found references to "ISDL Instruction Set Description Language".

Everything seems to be proprietary.

[MitchAlsup]

Wondering::

Back in 1983-1998 I worked with a set of tools from (can't remember) who
later got absorbed into Synopsis. They had a modeling language called M
and a Layout language called L. I am intimately familiar with L and not so
much with M. M is equivalent to unsynthesizeable Verilog while L is equivalent
to MacDraw with wires (like in Spice).

Maybe their name was "Silicon Compilers" with Tommy Ng as a principle
in the company (but not CEO or CTO at the time).

[EricP]

Some other related terms for searching:

"machine description language"

"application specific instruction set processors" (ASIP)
https://en.wikipedia.org/wiki/Application-specific_instruction_set_processor

Apparently some free, open tools from MIT to generate
Transport Triggered Architecture (TTA):
https://en.wikipedia.org/wiki/Transport_triggered_architecture

TTA-based Co-design Environment (TCE) tools
http://openasip.org/

and in a related area, automatic generation of C compilers for ASIP's.

e.g.
Automatic C compiler generation from architecture description language ISAC
https://drops.dagstuhl.de/opus/volltexte/2011/3065/
https://core.ac.uk/download/pdf/62916138.pdf

I've also seen references to automatic generation of
pipelined processors but did not look into it. e.g.
https://scholar.google.com/scholar?hl=en&as_sdt=0%2C5&q=automatic+generation+of+pipelined+processor&oq=

Rapid exploration of pipelined processors through
automatic generation of synthesizable RTL models, 2003
https://www.cise.ufl.edu/research/cad/Publications/rsp03.pdf

Rapid generation of high-quality risc-v processors from
functional instruction set specifications, 2019
https://www.csl.cornell.edu/~zhiruz/pdfs/assist-dac2019.pdf

[JimBrakefield]

Synopsys ASIP tools use "nML" as their architecture description language.
Which came with Target. They bought Target Compiler Technologies in 2014:
https://electronics360.globalspec.com/article/4021/synopsys-buys-application-processor-pioneer

Some of the flavor of ASIP design:
https://www.design-reuse.com/articles/24082/asip-design-methodology.html

LISA appears to have "paused"
The ArchC literature has active web pages:
https://github.com/ArchC/ArchC
and detailed models of several uP: https://github.com/ArchC

[Theo Markettos]

We have a flow where you write BSV (Bluespec SystemVerilog, open source) in
the style of an ISA definition manual, and that turns into synthesisable
(mostly unpipelined) RTL.

For a RISC-V implementation example:
https://github.com/CTSRD-CHERI/RVBS

We haven't quite got the flow where you generate that from the ISA
specification (in Sail, which is the RISC-V formal specification language)
but there isn't a big semantic difference. A few corner cases are a bit
awkward, eg having to deal with external memories where you need to go
multi-cycle.

I'm sure there are others out there...

Theo

[Al Grant]

On Monday, February 8, 2021 at 4:30:38 PM UTC, Theo Markettos wrote:

Can you prove equivalence of the Sail and BSV specifications?
I'd expect that defining a specific implementation - as a pipeline,
possibly with out of order execution etc. - would need a lot
of creative input and design tradeoffs, and that the challenge is
to prove equivalence with the original ISA spec throughout this
process. As opposed to generating an out-of-order superscalar
core mechanically from an ISA spec.

> I'm sure there are others out there...

There's ARM's Architecture Specification Language.

[Theo Markettos]

Al Grant <algra...@gmail.com> wrote:
> Can you prove equivalence of the Sail and BSV specifications?

Not in a formal sense. I think that would also first need a specification
of the semantics of BSV.

> I'd expect that defining a specific implementation - as a pipeline,
> possibly with out of order execution etc. - would need a lot
> of creative input and design tradeoffs, and that the challenge is
> to prove equivalence with the original ISA spec throughout this
> process. As opposed to generating an out-of-order superscalar
> core mechanically from an ISA spec.

This isn't intended for a performant implementation. It generates 'an'
implementation - one that functions and can be synthesised. You can then
use that as a golden model and run it in tandem verification with your
superscalar core.

Being simpler and (to some degree) automatically generated makes it less
error prone than writing your golden model by hand. However you would still
need to tandem verify your golden model against the specification since your
automatic generation could also be faulty.

> > I'm sure there are others out there...
>
> There's ARM's Architecture Specification Language.

Are there any backend tools to generate implementations for that?
(Sail can consume it, but it doesn't generate RTL)

Theo

[Mark Kaplan]

The company was originally called Silicon Design Labs. It later became Silicon Compilers and was finally purchased by Mentor Graphics.
I worked for Tommy when I first started.