Major differences between MIPS and ARM
aerosmith
Could anyone give me some differences between MIPS and the ARM
architecture. I am not looking for very low (close to hardware) level
information but just to know which architecture has/lacks what features.
Thanks in advance.
j...@beniston.com
> Could anyone give me some differences between MIPS and the ARM
> architecture. I am not looking for very low (close to hardware) level
> information but just to know which architecture has/lacks what features.
Here's a few little things:
More GPR in MIPS. Special purpose multiply registers in MIPS. Register
banking in ARM. Predicated instructions in ARM. Stoopid barrel shifter
for one operand in ARM.
Cheers,
Jon
Paul A. Clayton
[snip]
> More GPR in MIPS. Special purpose multiply registers in MIPS. Register
> banking in ARM. Predicated instructions in ARM. Stoopid barrel shifter
> for one operand in ARM.
Don't MIPS' Shadow Register Sets act similar to ARM's banked registers
(i.e., providing some registers for interrupt contexts--except with
MIPS it is
a full set of 31 GPRs)?
Also I don't think ARM has a branch/jump delay slot, correct?
ARM also has a load/store multiple registers instruction, correct?
ARM defines the Program Counter as a GPR.
I don't think ARM reserves a hard-wired-to-zero register (as MIPS
certainly does).
Paul A. Clayton
one who never really looked at the ARM ARM
but who has a minimal familiarity with MIPS
Torben Ægidius Mogensen
> j...@beniston.com wrote:
> [snip]
>> More GPR in MIPS. Special purpose multiply registers in MIPS. Register
>> banking in ARM. Predicated instructions in ARM. Stoopid barrel shifter
>> for one operand in ARM.
Why stupid?
> Also I don't think ARM has a branch/jump delay slot, correct?
Correct.
> ARM also has a load/store multiple registers instruction, correct?
Correct.
> ARM defines the Program Counter as a GPR.
Correct.
> I don't think ARM reserves a hard-wired-to-zero register (as MIPS
> certainly does).
Correct.
Also:
- ARM has condition flags (x86-style) where MIPS has branch-equal /
branch-not-equal instructions and for more complex comparisons
needs to set condition codes in GPRs (using set-less-than, etc.)
and test these by BEQ/BNE.
- ARM has auto-increment/decrement on load/store instructions and can
scale register-based offsets.
- ARM has a carry flag that makes multi-word integers easy to handle.
Torben
Tim McCaffrey
Interrupt handling, address modes, PSW (or not), # GPRs, floating point, size
of GPRs, where IP is located (one of GPRs or not), how long constants are
loaded.
The biggest difference between the two, from a higher level, is probably
floating point and addressing size: MIPS64 implementations usually
have floating point, and can address > 4G easily. ARM's support for FP is
limited, and usually not included, and it is a 32 bit architecture.
From an embedded point of view, the other difference might be that you don't
have to turn paging on with the MIPS to enable the cache.
- Tim
j...@beniston.com
Torben Ægidius Mogensen wrote:
> "Paul A. Clayton" <paaron...@earthlink.net> writes:
>
> > j...@beniston.com wrote:
> > [snip]
> >> More GPR in MIPS. Special purpose multiply registers in MIPS. Register
> >> banking in ARM. Predicated instructions in ARM. Stoopid barrel shifter
> >> for one operand in ARM.
>
> Why stupid?
Feature added because it was probably for free in original
implementation, but now complicates pipeline design, costing area /
performance.
Cheers,
Jon
Wilco Dijkstra
<j...@beniston.com> wrote in message
news:1165870007....@16g2000cwy.googlegroups.com...
You always need some kind of shifter, so it doesn't really need any
extra area. And since it doesn't need to be in the same pipestage as
the ALU, it doesn't reduce maximum clock frequency (it may actually
improve clock frequency as the ALU MUX is smaller MUX). So the
overall cost is small while the benefit is still significant (eg. encryption
is twice as fast).
The only shifted operations that are not very useful are loads with shifts
other than left shift of 0, 1, 2, 3. It's extremely rare to get anything
else,
and effective address generation is quite critical, so Thumb-2 doesn't
support any other shifts on loads/stores.
Wilco
j...@beniston.com
> > implementation, but now complicates pipeline design, costing area /
> > performance.
>
> You always need some kind of shifter, so it doesn't really need any
> extra area. And since it doesn't need to be in the same pipestage as
> the ALU, it doesn't reduce maximum clock frequency (it may actually
> improve clock frequency as the ALU MUX is smaller MUX). So the
> overall cost is small while the benefit is still significant (eg. encryption
> is twice as fast).
I think you are seriously underestimating the impact of an extra
pipeline stage which this requires.
Cheers,
Jon
Wilco Dijkstra
<j...@beniston.com> wrote in message
news:1165883219....@f1g2000cwa.googlegroups.com...
Why? The extra pipestage naturally allows for a skewed ALU to
reduce load latency, so it works out extremely well. The shift stage
is also used for complex operations (such as bitfield/SIMD), so
even if the shifter wasn't there, you would still need it. Every ARM
since ARM11 has implemented it after I proposed this combination.
Wilco
j...@beniston.com
> Why? The extra pipestage naturally allows for a skewed ALU to
> reduce load latency, so it works out extremely well. The shift stage
> is also used for complex operations (such as bitfield/SIMD), so
> even if the shifter wasn't there, you would still need it. Every ARM
> since ARM11 has implemented it after I proposed this combination.
But ARM make all their money of 7's and 9's right?
Cheers,
Jon
Wilco Dijkstra
<j...@beniston.com> wrote in message
news:1165914705.8...@80g2000cwy.googlegroups.com...
Not anymore. ARM7 and 9 provide less than 30% of total revenues.
In terms of volume they still represent ~99% of all ARMs sold, but they
are being replaced by newer cores.
ARM9 does 600MHz on a 90nm process - faster than the fastest cores
from MIPS. So your assertion the shifter slows these cores down is
mistaken (otherwise MIPS' cores would be twice as fast as ARM's).
Memory is far more speed critical than logic on modern processes.
Wilco
j...@beniston.com
> In terms of volume they still represent ~99% of all ARMs sold, but they
> are being replaced by newer cores.
Fair enough. 'Twas 70% last time I read a report.
> ARM9 does 600MHz on a 90nm process - faster than the fastest cores
> from MIPS. So your assertion the shifter slows these cores down is
> mistaken (otherwise MIPS' cores would be twice as fast as ARM's).
Well, that's not really a fair comparison, is it? MIPS could be worse
for many other reasons.
What would be fairer would be an ARM9 with and without the ability to
shift an operand.
> Memory is far more speed critical than logic on modern processes.
Agreed.
Cheers,
Jon
Wilco Dijkstra
<j...@beniston.com> wrote in message
news:1165930119.4...@73g2000cwn.googlegroups.com...
>> Not anymore. ARM7 and 9 provide less than 30% of total revenues.
>> In terms of volume they still represent ~99% of all ARMs sold, but they
>> are being replaced by newer cores.
>
> Fair enough. 'Twas 70% last time I read a report.
It dropped rapidly in just a few years, but I imagine it will level out due
to
royalties growing fast and taking over the loss in licensing revenues.
Basically everybody who wanted to license ARM7 has already done so.
>> ARM9 does 600MHz on a 90nm process - faster than the fastest cores
>> from MIPS. So your assertion the shifter slows these cores down is
>> mistaken (otherwise MIPS' cores would be twice as fast as ARM's).
>
> Well, that's not really a fair comparison, is it? MIPS could be worse
> for many other reasons.
Agreed. But MIPS is a bit purer than ARM so one could argue that
should translate into higher performance for a similar pipeline (MIPS
does have a similar range of embedded CPUs).
> What would be fairer would be an ARM9 with and without the ability to
> shift an operand.
Sure, but such a comparison isn't available. Even if it did enable
higher clock speeds, you would lose performance due to needing
extra shift instructions. So to get the same performance you need
more MHz which means increased power consumption.
Wilco
Tim McCaffrey
Wilco_dot...@ntlworld.com says...
>
>
><j...@beniston.com> wrote in message
>news:1165930119.4...@73g2000cwn.googlegroups.com...
>>> Not anymore. ARM7 and 9 provide less than 30% of total revenues.
>>> In terms of volume they still represent ~99% of all ARMs sold, but they
>>> are being replaced by newer cores.
>>
>> Fair enough. 'Twas 70% last time I read a report.
>
>It dropped rapidly in just a few years, but I imagine it will level out due
>to
>royalties growing fast and taking over the loss in licensing revenues.
>Basically everybody who wanted to license ARM7 has already done so.
>
>>> ARM9 does 600MHz on a 90nm process - faster than the fastest cores
>>> from MIPS. So your assertion the shifter slows these cores down is
>>> mistaken (otherwise MIPS' cores would be twice as fast as ARM's).
>>
>> Well, that's not really a fair comparison, is it? MIPS could be worse
>> for many other reasons.
>
processor (complete with PCI-X bus, DRAM controller, and LAN taps). Perhaps a
more "fair" comparison. (750 MHz dual core was available about the same time
as ARM9).
- Tim
Wilco Dijkstra
"Tim McCaffrey" <timca...@aol.com> wrote in message
news:elmue5$5sb$1...@trsvr.tr.unisys.com...
We were talking about ARM9 class CPUs and comparing with MIPS32
CPUs as these are also 32-bit mid-end embedded with similar pipelines
(~5 stage single in-order issue). The Broadcom chip is a high-end 64-bit
chip - much larger and power hungry. Not really fair...
Perhaps the most impressive result is the Samsung ARM10 at 1.2GHz
which has the shifter in series with the ALU. That is good evidence that
the shifter does not limit performance on ARM at all.
Wilco
Tim McCaffrey
Wilco_dot...@ntlworld.com says...
>> Broadcom sells a 1.2GHz, multicore, superscalar MIPS64 (with full FP)
>> embedded
>> processor (complete with PCI-X bus, DRAM controller, and LAN taps).
>> Perhaps a
>> more "fair" comparison. (750 MHz dual core was available about the same
>> time
>> as ARM9).
>
>We were talking about ARM9 class CPUs and comparing with MIPS32
>CPUs as these are also 32-bit mid-end embedded with similar pipelines
>(~5 stage single in-order issue). The Broadcom chip is a high-end 64-bit
>chip - much larger and power hungry. Not really fair...
>
>Perhaps the most impressive result is the Samsung ARM10 at 1.2GHz
>which has the shifter in series with the ALU. That is good evidence that
>the shifter does not limit performance on ARM at all.
>
>Wilco
>
>
Ok, I was responding to the statement "ARM9 does 600MHz on a 90nm process -
faster than the fastest cores from MIPS." Which does not say anything about
power or size.
- Tim
aerosmith
Thank you very much for the information. It was really helpful.
azhar...@gmail.com
what about the datapath of ARM architecture, how is it different from that of MIPS?
Thanks