Cray-I basic gates

[Thomas Koenig]

[xpost to comp.arch and ald.folklore.computers, f-up to
comp.arch]

Reading literature on the Cray-I, one finds that their logic was
implemented in ECL using 5/4 NAND gates.

Wikipedia claims that these were, in fact, XOR gates, but the only
source to that claim is a link to a datasheet, without a source
stating that this chip was indeed used in the Cray-1, so I am
disinclined to believe that (and I may just remove it as being
unsourced, and in contradiction to published literature).

The pictures of circuit boards that I found that were big enough
to read the markings only had the flip-flops and the static ROMs
on them.

So, does anybody have an idea of what they actually used (and
maybe a source)?

[Brian G. Lucas]

I'm pretty sure that the NAND gates and Flip-Flops were
Motorola ECL. I remember Motorolans from Austin talking
about how they hated going to Chippewa Falls in the winter.

[MitchAlsup1]

Thomas Koenig wrote:

> [xpost to comp.arch and ald.folklore.computers, f-up to
> comp.arch]

> Reading literature on the Cray-I, one finds that their logic was
> implemented in ECL using 5/4 NAND gates.

CRAY-1 was built with (IIRC) dual 4 input OR/NOR gates MECL-III 1660
The flip-flop chips MECL-III 1666, the random access memory cell
MECL-III 1680, and the quad line receiver MECL-III 1692. If an XOR
gate was used, it was only in the FP multiplier. These are from my
1969 MECL data book. One interesting factoid:: the 1975 MECL book
has 11 pages of how the flip-flop was tested, whereas the 19769
book only has 2 pages of how this chip was tested. My guess is
CRAY found a testing anomaly in the Motorola Factory on this part.

More interestingly, Cray-1 had 4 lengths of wire--1 foot, 2-foot,
3-foot and 6-foot of RU58 coax. corresponding to roughly 2ns delay,
4ns delay, 6ns delay, and 1 clock of wire delay.

ECL gates are inherently NOR logic and come with True and Complement
outputs. {{NOR assumes you think -0.8V is high and -2.0V is low--if
you think -0.8 is low than they are NAND gates.}}

An ECL NOR gate is a differential amplifier with an emitter follower
output gate.

An ECL NAND gate is a stack of differential amplifiers with emitter
follower level shifters for the lower differential amplifiers and
emitter follower output gates. These NAND gates are slower (20%-30%)
than NOR gates, so logic designers learn how to use the inverted outputs
of the NOR gates, except in certain circumstances. ECL NAND gates are
often used as linear modulators.....

> Wikipedia claims that these were, in fact, XOR gates, but the only
> source to that claim is a link to a datasheet, without a source
> stating that this chip was indeed used in the Cray-1, so I am
> disinclined to believe that (and I may just remove it as being
> unsourced, and in contradiction to published literature).

This is incorrect. An ECL XOR gate is much like a NAND gate and even
slower. The Gallium Arsenide machine Seymour was working on after
leaving CRAY had this XOR characteristic.

> The pictures of circuit boards that I found that were big enough
> to read the markings only had the flip-flops and the static ROMs
> on them.

> So, does anybody have an idea of what they actually used (and
> maybe a source)?

See above:: to anyone in the Austin Tx. area:: I have these books
and you can come an read them if you like. I may have some old
CRAY literature, too.

[John Levine]

According to MitchAlsup1 <mitch...@aol.com>:

>> So, does anybody have an idea of what they actually used (and
>> maybe a source)?

Bitsavers has some manuals like this one:

https://bitsavers.org/pdf/cray/CRAY-1/2240004C_CRAY-1_Hardware_Reference_Nov77.pdf

Section 2 describes the various chip types.

--
Regards,
John Levine, jo...@taugh.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly