Moore's second law

[Tim Rentsch]

For everyone's interest and possible reading pleasure

https://www.newyorker.com/tech/annals-of-technology/the-worlds-largest-computer-chip

[Marcus]

On 2021-08-29 05:45, Tim Rentsch wrote:
> For everyone's interest and possible reading pleasure
>
> https://www.newyorker.com/tech/annals-of-technology/the-worlds-largest-computer-chip
>

It's interesting how Tesla took a very similar approach with their DOJO
AI chip. It's 25 processors, 645 mm^2 each, on a single "chip" (which
should mean over 16000 mm^2).

https://www.tomshardware.com/uk/news/tesla-d1-ai-chip

https://www.cnbc.com/2021/08/19/tesla-unveils-dojo-d1-chip-at-ai-day.html

https://en.wikipedia.org/wiki/Tesla_Dojo

/Marcus

[John Levine]

According to Marcus <m.de...@this.bitsnbites.eu>:

>On 2021-08-29 05:45, Tim Rentsch wrote:
>> For everyone's interest and possible reading pleasure
>>
>> https://www.newyorker.com/tech/annals-of-technology/the-worlds-largest-computer-chip
>
>It's interesting how Tesla took a very similar approach with their DOJO
>AI chip. It's 25 processors, 645 mm^2 each, on a single "chip" (which
>should mean over 16000 mm^2).

In retrospect the world seems to have over-learned the lesson of Trilogy's failure,
that you can't make a chip that big, which you can't if the whole thing has to work.

Once you realize that a bunch of identical elements on a single chip
can communicate a lot faster than separate chips, and if they are all
the same, they don't all have to work and you can route around the bad
ones, the story writes itself.

For me the amazing part is that Cerebras manages to pump 15KW into the
chip and then pump it out. There's nothing new about water cooling
which IBM used in the 1960s nor about computers that use a lot of
power, but pumping that much power into something that small and not
creating fireworks is very impressive. By comparison, an arc welder
uses about 10KW.

--
Regards,
John Levine, jo...@taugh.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly

[Quadibloc]

On Tuesday, August 31, 2021 at 11:14:58 AM UTC-6, John Levine wrote:

> Once you realize that a bunch of identical elements on a single chip
> can communicate a lot faster than separate chips, and if they are all
> the same, they don't all have to work and you can route around the bad
> ones, the story writes itself.

They were going to use a wafer-scale memory chip as a peripheral for the
Sinclair QL, but the company making that one *also* failed, so making very
large chips even when they were built of multiple identical components
was _also_ profoundly challenging.

Trilogy was not the only "wafer-scale" failure, and most, perhaps, all of
the others _were_ using massive redundancy.

John Savard

[Quadibloc]

I see my memory has played tricks on me. Apparently there was only
one Anamartic, not about half a dozen similar companies.

John Savard

[Theo Markettos]

Quadibloc <jsa...@ecn.ab.ca> wrote:
> On Tuesday, August 31, 2021 at 11:14:58 AM UTC-6, John Levine wrote:
>
> > Once you realize that a bunch of identical elements on a single chip
> > can communicate a lot faster than separate chips, and if they are all
> > the same, they don't all have to work and you can route around the bad
> > ones, the story writes itself.
>
> They were going to use a wafer-scale memory chip as a peripheral for the
> Sinclair QL, but the company making that one *also* failed, so making very
> large chips even when they were built of multiple identical components
> was _also_ profoundly challenging.

http://www.computinghistory.org.uk/det/3043/Anamartic-Wafer-Scale-160MB-Solid-State-Disk/

"The Wafer Stack has a Nat-ive Mode Interface and optional SCS interface: the
native mode interface has access time of 200 microseconds and average
transfer rate of 1.6Mbytes-per-second, 5Mbytes burst. With SCSI, access time
is under 1mS with average transfer rate of 3Mbytes-per-second. Power
consumption is a hefty 42W maximum at 5.25v and forced air cooling is
needed. Designed in an 8-inch form factor the Wafer Stack can contain up to
eight wafers - four storage modules, for 160Mb capacity. OEM samples,
including wafer controller and SCSI cost $11,680 for the 40Mb version,
$33,590 for 160Mb. Anamartic sees the Wafer Stack being used particularly in
high-volume transaction processing systems."


Contemporary HDD was about 20ms latency, so that's a fair bit better. But
transfer rate sounds awful - for comparison a 3.5" HD floppy disc was
250KB/s. You could stick 8 floppy drives in parallel and get the same
transfer rate.

Theo