Reducing Latency -- Reducing Size of Larger Data Structures

[Casey Hawthorne]

An idea to reduce memeory latency, is to have a complex dual/quad/etc.
core CPU surrounded by four or more simpler CPUs.
The simpler CPUs have a simpler instruction set and do less context
switching.
So any operations (e.g. folding, filtering) that reduce the size of a
larger data structure and that can be done on the simpler CPU
instruction sets are shunted off to the simpler CPUs.

So, the complex CPUs receive less data and therefore can have better
cacheing performance, less latency and better throughput.

--
Regards,
Casey

[Peter Grandi]

> An idea to reduce memeory latency, is to have a complex
> dual/quad/etc. core CPU surrounded by four or more simpler
> CPUs. The simpler CPUs have a simpler instruction set and do
> less context switching.

Let's call them peripheral processors :-).

> So any operations (e.g. folding, filtering) that reduce the size
> of a larger data structure and that can be done on the simpler
> CPU instruction sets are shunted off to the simpler CPUs.

Let's call that the IBM's Broadband Engine (aka in a variant as
the Cell):

http://www.research.ibm.com/cell/

> So, the complex CPUs receive less data and therefore can have
> better cacheing performance, less latency and better throughput.

And a more complex programming model, ask PS/3 programmers.