Comparison of cache line sizes

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James Harris

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Dec 11, 2008, 6:48:46 AM12/11/08
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Does anyone know of a web page containing a comparison of cache line
sizes on different architectures? Just the reasonably popular ones
would do. If necessary I could download the docs and make up my own
table but I can't help feeling someone out there on the Internet has
done this already.

It's mainly instruction cache lines that I am interested in but it
wouldn't hurt to know those for data caches too if they are
different....

Wikipedia

http://en.wikipedia.org/wiki/CPU_cache

states that cache line sizes go up as high as 512 bytes. That seems
unreasonably high. Does anyone know what machine or machines that
applies to?

James

MitchAlsup

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Dec 11, 2008, 10:51:14 PM12/11/08
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On Dec 11, 5:48 am, James Harris <james.harri...@googlemail.com>
wrote:

Athlon and Opteron use 512 bit cache lines and I'm sure a few more.
many (many) machines use 256 bit cache lines
early cached 32 bit machines would have used 128 bit cache lines

This is a delicate balance between latency and bandwidth; and another
delicate balance between true and false sharing. And there is no 1
optimal line size.

Rick Jones

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Dec 11, 2008, 11:49:36 PM12/11/08
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Itanium uses a 128 byte cache line. I think Power[56] uses something
in that range as well. No idea about various SPARC processors.

rick jones
--
portable adj, code that compiles under more than one compiler
these opinions are mine, all mine; HP might not want them anyway... :)
feel free to post, OR email to rick.jones2 in hp.com but NOT BOTH...

James Harris

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Dec 12, 2008, 6:06:24 AM12/12/08
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On 12 Dec, 03:51, MitchAlsup <MitchAl...@aol.com> wrote:
> On Dec 11, 5:48 am, James Harris <james.harri...@googlemail.com>
> wrote:
>
>
>
> > Does anyone know of a web page containing a comparison of cache line
> > sizes on different architectures? Just the reasonably popular ones
> > would do. If necessary I could download the docs and make up my own
> > table but I can't help feeling someone out there on the Internet has
> > done this already.
>
> > It's mainly instruction cache lines that I am interested in but it
> > wouldn't hurt to know those for data caches too if they are
> > different....
>
> > Wikipedia
>
> > http://en.wikipedia.org/wiki/CPU_cache
>
> > states that cache line sizes go up as high as 512 bytes. That seems
> > unreasonably high. Does anyone know what machine or machines that
> > applies to?
>
> Athlon and Opteron use 512 bit cache lines and I'm sure a few more.
> many (many) machines use 256 bit cache lines
> early cached 32 bit machines would have used 128 bit cache lines
>
> This is a delicate balance between latency and bandwidth; and another
> delicate balance between true and false sharing. And there is no 1
> optimal line size.

It's unusual to see cache line sizes written in bits ... but if you
prefer that then the Wikipedia article says cache line sizes go as
high as 4096 bits.

Whichever way you write it that's a large line size. I wonder which
machine(s) it applies to. Maybe a supercomputer? It's not the Cray X1
anyway.

http://docs.cray.com/books/S-2315-50/html-S-2315-50/x5129.html

That uses 32 bytes (or 256 bits if you prefer).

I wonder if the Wikipedia article is right. I may add a citation-
needed tag to it.

James

James Harris

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Dec 12, 2008, 8:01:11 AM12/12/08
to

Someone e-mailed this to me directly rather than posting here. Perhaps
he receives Usenet via an email gateway. I don't know. At any rate I
presume he prefers his name and organisation not to be included so I
am posting his reply here anonymously.

To the person who sent me this: thank you. You know who you are. :-)

-----
1) Most if not all of the MIPS processors used by SGI had 128 byte
line sizes (the
R8000 processor may have used a large cache line size with 128
byte segments).

2) The IBM Power 2 processor I believe used 256 byte line sizes.
This probably
included the P2SC.

3) The IBM Power 3 processors (all four variants) used 128 byte line
sizes.

4) The IBM Power 4/Power 4+ processor used 128 byte line sizes for
the
L1 and L2 cache, and a 512 byte line size with 128 byte segment
size
for the L3 cache. (Don't know about more recent IBM processors).

5) I think that all of the ALPHA processors used a 64 byte line size.

6) All of the HP PA-RISC 8XXX processors used a 64 byte line size.
Earlier HP PA-RISC processors used either 32 byte or 64 byte line
sizes (check on a per processor basis if you really care).

7) I think that the Motorola 68020 and beyond used 32 byte line
sizes.

8) Intel X86 processors starting with the 486 used 32 byte line
sizes.
I think that more recent versions use 64 byte line sizes, but am
not certain as to when they changed.

9) I think that all AMD Opteron processors and beyond use 64 byte
line sizes, but am not certain about older AMD processors.

10) Fairly certain that all Itanium processors use 64 byte line
sizes.

11) SUN UltraSPARC IIs used 64 byte line sizes.

12) SUN UltraSPARC IIIs used 64 byte L1 line sizes and I think 512
byte
L2 line sizes, with 64 byte segment sizes. Don't know about
more
recent UltraSPARC processors.
-----

James

j...@cix.compulink.co.uk

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Dec 13, 2008, 11:17:40 AM12/13/08
to
In article
<6c3fa445-3758-4e69...@p2g2000prf.googlegroups.com>,
james.h...@googlemail.com (James Harris) wrote:

> 8) Intel X86 processors starting with the 486 used 32 byte line
> sizes. I think that more recent versions use 64 byte line sizes,
> but am not certain as to when they changed.

NetBurst architecture ones use 128-byte cache lines. Core, Core 2, and
so on use 64-byte lines.

> 10) Fairly certain that all Itanium processors use 64 byte line
> sizes.

128 byte IIRC

--
John Dallman, j...@cix.co.uk, HTML mail is treated as probable spam.

nedbrek

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Dec 13, 2008, 2:52:14 PM12/13/08
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Hello all,

<j...@cix.compulink.co.uk> wrote in message
news:1fmdnYSpVdK5fd7U...@giganews.com...


> In article
> <6c3fa445-3758-4e69...@p2g2000prf.googlegroups.com>,
> james.h...@googlemail.com (James Harris) wrote:
>
>> 8) Intel X86 processors starting with the 486 used 32 byte line
>> sizes. I think that more recent versions use 64 byte line sizes,
>> but am not certain as to when they changed.
>
> NetBurst architecture ones use 128-byte cache lines. Core, Core 2, and
> so on use 64-byte lines.

The NetBurst lines are two way sectored (64 byte sectors). The other sector
is treated as a prefetch. So, the cache is tagged to 128 byte, but the bus
transaction units are all 64 byte... Core 2 may be the same, I forget...

>> 10) Fairly certain that all Itanium processors use 64 byte line
>> sizes.
>
> 128 byte IIRC

Confirmed. All modern Itaniums are 128 byte (Merced might of been 64, that
is going way back :).

Ned


Terje Mathisen

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Dec 13, 2008, 4:31:29 PM12/13/08
to
j...@cix.compulink.co.uk wrote:
> In article
> <6c3fa445-3758-4e69...@p2g2000prf.googlegroups.com>,
> james.h...@googlemail.com (James Harris) wrote:
>
>> 8) Intel X86 processors starting with the 486 used 32 byte line
>> sizes. I think that more recent versions use 64 byte line sizes,
>> but am not certain as to when they changed.
>
> NetBurst architecture ones use 128-byte cache lines. Core, Core 2, and

Doesn't NetBurst split each 128-byte line into two segments, which can
be loaded independently?

Terje
--
- <Terje.M...@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"

wind...@gmail.com

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Dec 14, 2008, 6:12:47 AM12/14/08
to
> On 11 Dec, 11:48, James Harris <james.harri...@googlemail.com> wrote:
> 7)  I think that the Motorola 68020 and beyond used 32 byte line
> sizes.
>

All 68020++ systems use 16 byte per cache line with the following
sizes:

020: 256 inst direct mapped
030: 256 inst, 256 data; both direct mapped
040: 4k inst, 4k data; both 4 set associative
060: 8k inst, 8k data; both 4 set associative

on 040 and 060 you can use the MOVE16 instruction to do memory-to-
memory bulk copies without polluting the data cache, since it does a
direct whole line read and whole line write and never reads the
destination line.


Chris M. Thomasson

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Dec 14, 2008, 1:28:48 PM12/14/08
to
"Terje Mathisen" <terje.m...@hda.hydro.com> wrote in message
news:L-adnVoPvakvtNnU...@giganews.com...

> j...@cix.compulink.co.uk wrote:
>> In article
>> <6c3fa445-3758-4e69...@p2g2000prf.googlegroups.com>,
>> james.h...@googlemail.com (James Harris) wrote:
>>
>>> 8) Intel X86 processors starting with the 486 used 32 byte line
>>> sizes. I think that more recent versions use 64 byte line sizes, but am
>>> not certain as to when they changed.
>>
>> NetBurst architecture ones use 128-byte cache lines. Core, Core 2, and
>
> Doesn't NetBurst split each 128-byte line into two segments, which can be
> loaded independently?

Yes.

Chris M. Thomasson

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Dec 14, 2008, 1:31:03 PM12/14/08
to
"James Harris" <james.h...@googlemail.com> wrote in message
news:6c3fa445-3758-4e69...@p2g2000prf.googlegroups.com...

> On 11 Dec, 11:48, James Harris <james.harri...@googlemail.com> wrote:
>> Does anyone know of a web page containing a comparison of cache line
>> sizes on different architectures? Just the reasonably popular ones
>> would do. If necessary I could download the docs and make up my own
>> table but I can't help feeling someone out there on the Internet has
>> done this already.
>>
>> It's mainly instruction cache lines that I am interested in but it
>> wouldn't hurt to know those for data caches too if they are
>> different....
>>
>> Wikipedia
>>
>> http://en.wikipedia.org/wiki/CPU_cache
>>
>> states that cache line sizes go up as high as 512 bytes. That seems
>> unreasonably high. Does anyone know what machine or machines that
>> applies to?
>
> Someone e-mailed this to me directly rather than posting here. Perhaps
> he receives Usenet via an email gateway. I don't know. At any rate I
> presume he prefers his name and organisation not to be included so I
> am posting his reply here anonymously.
>
> To the person who sent me this: thank you. You know who you are. :-)
>
> -----
[...]

>
> 12) SUN UltraSPARC IIIs used 64 byte L1 line sizes and I think 512
> byte
> L2 line sizes, with 64 byte segment sizes. Don't know about
> more
> recent UltraSPARC processors.
> -----

UltraSPARC T1 use 64-byte L2 cache line:


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https://coolthreads.dev.java.net/servlets/ProjectForumMessageView?messageID=11473&forumID=1797

Tim McCaffrey

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Dec 17, 2008, 1:57:08 PM12/17/08
to
In article <6c3fa445-3758-4e69...@p2g2000prf.googlegroups.com>,
james.h...@googlemail.com says...
>

>8) Intel X86 processors starting with the 486 used 32 byte line
>sizes.
> I think that more recent versions use 64 byte line sizes, but am
> not certain as to when they changed.
>

The 486 has 16 byte cache lines. Interface to memory is 32 bits. The same
may also apply to the Pentium Overdrive.

- Tim

Alex Vinokur

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Jan 15, 2009, 2:10:26 AM1/15/09
to
On Dec 12 2008, 3:01 pm, James Harris <james.harri...@googlemail.com>
wrote:
[snip]

> 3)  The IBM Power 3 processors (all four variants) used 128 byte line
> sizes.
[snip]

Concrning IBM (AIX):

AIX 5.3

systemcfg.h File
Purpose
Defines the _system_configuration structure.

Description
The systemcfg.h file defines the _system_configuration structure. This
is a global structure that identifies system characteristics. The
system_configuration structure is provided in read-only system memory.
New fields will be added to the structure in future releases. The
attributes in the _system_configuration structure have the following
values:

[------- omitted ---------]

dcache_line
Contains the line size in bytes of L1 data cache.

L2_cache_size
Contains the size of the L2 cache in bytes. A value of 0 indicates no
L2 cache is present.


// ------------- Test program ----

#include <iostream>

#include <sys/systemcfg.h>

main()
{
std:: cout << _system_configuration.dcache_line <<
std::endl;

std:: cout << _system_configuration.L2_cache_size <<
std::endl;

return 0;

}

Output:

128 // L1
0 // L2


Alex Vinokur


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