OK Xilinx users, it's time I was let in on the joke...
Mark McDougall
to go postal in the lobby of Xilinx HQ. I don't expect perfection but this
really is beyond a joke.
Can someone please put me out of my misery, and finally admit that you
have _all_ been having me on for the past few years now! :O ...that it has
all been an elaborate hoax instigated by someone I offended in a past
life. ...that a team of engineers has been working for years to produce an
IDE that crashes randomly, and steadfastly refuses to launch tools on
Tuesday mornings and Friday afternoons? ...working for years on a
synthesizer that removes random bits of logic, or sits spinning in an
infinite loop on an entity that works in another project? ...that corrupts
my project file bi-monthly.
And worst of all - _you_ lot, telling me that Xilinx actually works, and
that you _can_ use it for more than flashing LEDs on the Spartan starter
kit. And I was gullible enough to believe you! :O :(
I've seen the light. You _cannot_ convince me that it is possible to
produce a commercial product in silicon using these tools. Period.
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Antti
Mark,
you are taking it one level higher than I, I think i have said in
public
years ago that Xilinx has totally lost control over its software
development
and that their tools would come "completly unuseable" by the time 40nm
FPGA's come out to the market (unless they FIX their software
development flow!)
well Xilinx 40nm FPGA's are not yet on stock at digikey, so based on
that
and on my prediction Xilinx has still time to reach the complete
useless
status with their software
Antti
luudee
> I've had it up to the eyeballs with Xilinx tools now. I'm seriously ready
> to go postal in the lobby of Xilinx HQ. I don't expect perfection but this
> really is beyond a joke.
...
> I've seen the light. You _cannot_ convince me that it is possible to
> produce a commercial product in silicon using these tools. Period.
>
> Regards,
>
> --
> Mark McDougall, Engineer
Hi Mark,
I know these things can be really frustrating, but since IDE/EDK
11 I must say I have been quite happy. I should note that I am
a Linux user, and don't have the traditional Windows crap to deal
with.
I am now using 11.3, and my only concern is when they will force
me use the software SDK next release ... that's something I don't
look forward too ...
Perhaps if you can try to describe your problem in greater detail,
somebody might have a suggestion. Could you be running out of
memory or disk space ?
Cheers,
rudi
HT-Lab
"Mark McDougall" <ma...@vl.com.au> wrote in message
news:7JmdnUcpQOJNI27X...@westnet.com.au...
Yep, using EDA software is like using a small leaking boot trying to cross a
violent river. All EDA software has bugs and some of them are intelligent enough
to strike when you stress level is at its maximum. Unfortunately this will never
change since software is getting more complex, market pressure is increasing,
engineers expectations are increasing, weather is getting worse, mentality to
produce quality work is diminishing, more complex devices, more annoying TV
commercials etc etc.
The only mild remedy against this whirlpool of misery is good technical support.
Luckily I found that Xilinx has good support so logs those bugs, make sure they
fix them, use gotomeeting/webex/etc to show what is happening if you can't send
out any code. If they don't respond than splash out on
newsgroups/facebook/linkin/blogs/twitter or whatever the communication flavour
of the month is. I am sure that no EDA vendor can handle a constant stream of
bad publicity.
As they say, life is a bitch and then you have to use EDA tools......
Hans
www.ht-lab.com
Oscar Almer
Mark McDougall <ma...@vl.com.au> wrote:
> I've had it up to the eyeballs with Xilinx tools now. I'm seriously
> ready to go postal in the lobby of Xilinx HQ. I don't expect
> perfection but this really is beyond a joke.
>
> Can someone please put me out of my misery, and finally admit that you
> have _all_ been having me on for the past few years now! :O ...that
> it has all been an elaborate hoax instigated by someone I offended in
> a past life. ...that a team of engineers has been working for years
> to produce an IDE that crashes randomly, and steadfastly refuses to
> launch tools on Tuesday mornings and Friday afternoons? ...working
> for years on a synthesizer that removes random bits of logic, or sits
> spinning in an infinite loop on an entity that works in another
> project? ...that corrupts my project file bi-monthly.
>
> And worst of all - _you_ lot, telling me that Xilinx actually works,
> and that you _can_ use it for more than flashing LEDs on the Spartan
> starter kit. And I was gullible enough to believe you! :O :(
>
> I've seen the light. You _cannot_ convince me that it is possible to
> produce a commercial product in silicon using these tools. Period.
>
I, at least, gave up on the ise wrapper about a year and a half ago -
it just didn't do it, anymore. Instead I drive the flow (xst, map, par,
etc) from a single makefile, and a short one at that - maybe 20 lines.
The things I know im missing out on is 1. the pretty XML reports and 2.
COREgen etc hook-ins. The former I can survive without, as its
easier to grep through plain text reports anyway, and the latter I
typically only need to run once anyway, at which point I suffer ise
long enough to move the generated files somewhere sensible.
Just my experience.
//Oscar
Curt Johnson
> I've had it up to the eyeballs with Xilinx tools now. I'm seriously ready
> to go postal in the lobby of Xilinx HQ. I don't expect perfection but this
> really is beyond a joke.
>
>
> I've seen the light. You _cannot_ convince me that it is possible to
> produce a commercial product in silicon using these tools. Period.
>
> Regards,
>
If it is any solace, the Mentor schematic capture and PCB routing tools
are much worse. In addition to continuous license issues, crashes,
version compatibility problems, and file corruption, they produce
unreliable output. I now have to manually check every trace on a 10
layer PCB with multiple BGA packages ever since we discovered that the
tools can randomly delete nets from a fully routed board without warning.
At lease ISE only causes frustration and project delays. I've never had
to scrap thousands of USD worth of materials because of them.
Curt
rickman
The reason for using commercial tools is supposed to be the great
support and the lack of serious bugs... so if you don't like your
expensive layout tools, why use them? I used FreePCB on my last
project and found it very suitable. I am sure there are some things
that you need to do manually that expensive tools might do
automatically, but hand checking all the nets is not one of them.
Not trying to be smart, this is a serious question.
Rick
LittleAlex
I thought that they fixed the problem by using the "entitle now"
software for downloading. ;)
If you can't download the software, you can't find the bugs. And even
if you -think- you've downloaded it, they can always claim that you
had a network issue.
Sadly, Xilinx is writing software that Americans will buy. Features
are more important than robustness. Flash is more important than
function. Sigh.
AL
PS: I too have given up on the GUI. I use it -once- per project to
get the initial setup, the rest of the time I use makefiles and
scripts.
Rob Gaddi
Hear hear. I've had very little trouble with the backend Xilinx tools,
but the GUI is absolute rubbish. Crashes constantly, takes PHENOMINAL
amounts of memory just to exist, and every release moves all of the
important options to somewhere new and exciting. I looked into using
TCL instead, but that just hides things inside of more magic boxes.
Makefiles just work; I switched over around ISE 8 and have never
thought of regretting it.
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Curt Johnson
> The reason for using commercial tools is supposed to be the great
> support and the lack of serious bugs... so if you don't like your
> expensive layout tools, why use them? I used FreePCB on my last
> project and found it very suitable. I am sure there are some things
> that you need to do manually that expensive tools might do
> automatically, but hand checking all the nets is not one of them.
>
> Not trying to be smart, this is a serious question.
>
> Rick
Good question. Mostly inertia.
If FreePCB will import our libraries and designs, I'll check it out in a
minute.
Maintenance is an issue. We are in the medical racket. Product lifetimes
can be a dozen years or more. We are still shipping product with
XC3142's in them. When parts go obsolete, we often need to quick turn a
board to keep shipping product. That means either we keep the tools
around for the duration, or find something that can read the files.
Most of my new designs are more or less 50% original and 50% cut and
pasted from previous designs. It saves a bit of time not having to
recreate parts and redraw schematics.
I've used Pads, Tango, Calay, Cadroid, Orcad, and a few other packages
over the years. Some were better than others, but all of them had
problems of one sort or another. I've kind of got to the point where if
my PC doesn't catch fire after I install a new version, I consider it a
victory.
Curt
Jon Elson
> And worst of all - _you_ lot, telling me that Xilinx actually works, and
> that you _can_ use it for more than flashing LEDs on the Spartan starter
> kit. And I was gullible enough to believe you! :O :(
>
> I've seen the light. You _cannot_ convince me that it is possible to
> produce a commercial product in silicon using these tools. Period.
Umm, we have been developing stuff for some time for mostly in-house use
here at Washington University, mostly using Virtex 2 stuff here. I also
have been doing some very UN-challenging units on both CPLDs and Spartan
2E FPGAs at Pico Systems, my "night job". You can see some of the
products I have developed at
http://pico-systems.com/oscrc4/catalog/index.php?cPath=3
for CNC motion control. Most of the boards on that page have either a
CPLD or an FPGA in them.
I have mostly moved development (at both sites) over to Linux and iSE
10.1. I do have an annoying problem where you can't print schematics
without some fooling around, but otherwise it seems to work well. I
only use schematics now on some interface-type CPLDs, so that's no big
deal. I still find their modelsim simulator cumbersome to use, but I
live with it. I understand they are phasing out the timing diagram
entry for sim stimulus, and I really prefer that to writing the test
bench in words.
Now, I have to admit, most of this stuff is NOT pushing the chips to the
ultimate. I am using 40 MHz clocks on the Spartan 2E, for instance!
I do have a CPLD design wehre I used every FF and every macrocell, and
any time I want to change something it is a great hassle, but it does
get it routed.
I have sold about 180 of the motion controller boards, so it is real
production to ME, at least!
Jon
malcolm
> If it is any solace, the Mentor schematic capture and PCB routing tools
> are much worse. In addition to continuous license issues, crashes,
> version compatibility problems, and file corruption, they produce
> unreliable output. I now have to manually check every trace on a 10
> layer PCB with multiple BGA packages ever since we discovered that the
> tools can randomly delete nets from a fully routed board without warning.
Err, but a random-deleted net is actually easy to find, as you usually
have more than one copy (as in, in the SCH, or even in a copy of the
PCB ) ?
Which Mentor flows/versions are you using ?
luudee
I used to do the same. And I still use the scripts when I just need
to recompile the entire thing because of an RTL change in my code.
But, since ISE 11, I have started to create MPD files and use EDK
to put together the system. The GUI is now (for me at least) very
stable, and reasonable easy to use. (This is all on linux).
I am even starting to support the EDK plugin for most of our IP
cores, as it seems to be actually working pretty well now.
Regards,
rudi
Nico Coesel
>I've had it up to the eyeballs with Xilinx tools now. I'm seriously ready
>to go postal in the lobby of Xilinx HQ. I don't expect perfection but this
>really is beyond a joke.
>
>Can someone please put me out of my misery, and finally admit that you
>have _all_ been having me on for the past few years now! :O ...that it has
>all been an elaborate hoax instigated by someone I offended in a past
>life. ...that a team of engineers has been working for years to produce an
>IDE that crashes randomly, and steadfastly refuses to launch tools on
>Tuesday mornings and Friday afternoons? ...working for years on a
>synthesizer that removes random bits of logic, or sits spinning in an
>infinite loop on an entity that works in another project? ...that corrupts
>my project file bi-monthly.
>
>And worst of all - _you_ lot, telling me that Xilinx actually works, and
>that you _can_ use it for more than flashing LEDs on the Spartan starter
>kit. And I was gullible enough to believe you! :O :(
>
>I've seen the light. You _cannot_ convince me that it is possible to
>produce a commercial product in silicon using these tools. Period.
Its about time someone writes a decent Eclipse plugin / makefile
generator.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
james
<curt.j...@dicombox.net> wrote:
|If it is any solace, the Mentor schematic capture and PCB routing tools
|are much worse. In addition to continuous license issues, crashes,
|version compatibility problems, and file corruption, they produce
|unreliable output. I now have to manually check every trace on a 10
|layer PCB with multiple BGA packages ever since we discovered that the
|tools can randomly delete nets from a fully routed board without warning.
|=============
Mentor was an expensive joke ten years ago and I am not so surprised
that it has not changed. I am glad I am retired and don't have to use
their tools.
james
rickman
FreePCB is not the sun and moon of PCB layout. It won't import any
other layouts or libraries I'm pretty sure. It is a pretty good
tool. Do *any* layout tools import other layouts? There have been
efforts over the years to establish a common format for schematic and
layout tools and it has always met with failure because none of the
tool vendors want to let a user switch easily. That alone is reason
enough for me to want to never use a commercial tool again.
Rick
-jg
> Do *any* layout tools import other layouts?
Yes, Mentor have Layout translators from Protel(Altium), Cadstar,
OrCAD, and also Schematic Translators from the same.
They work quite well, and are good for harvesting web resource,
and things like reference designs.
Last time I checked, Analog Devices and SiLabs used Mentor's
PADS for their designs, but others may use OrCAD Schematic.
DXF is also a useful interchange format, often overlooked.
I remember creating a good decal for an Open-Frame relay, via
the DXF file supplied.
In fact, the DXF file had vital info that was missing off the
drawing !!
-jg
Mike Harrison
>On Nov 9, 4:51�pm, rickman <gnu...@gmail.com> wrote:
>> �Do *any* layout tools import other layouts? �
>
> Yes, Mentor have Layout translators from Protel(Altium), Cadstar,
>OrCAD, and also Schematic Translators from the same.
>
> They work quite well, and are good for harvesting web resource,
>and things like reference designs.
>
> Last time I checked, Analog Devices and SiLabs used Mentor's
>PADS for their designs, but others may use OrCAD Schematic.
>
>DXF is also a useful interchange format, often overlooked.
But probably one of the least standard 'standards' out there, at least in terms of implementation...
I find that an imported/exported DXF rarely resembles the original in all respects - even really
basic stuff like the scale can be completely wrong!
rickman
Curt was asking about drawings and libraries. Do the converters also
convert user built libraries? A lot of people have significant
libraries which represent a lot of work although, if the info is
captured in a way that is easily read, I think most footprints are
pretty easy to recreate. It is coming up with the dimensions that is
the hard part I think. I know FreePCB makes it *very* easy to draw
footprints, it is just figuring out how to design them that is the
hard part. It would only be a weeks work to convert 100 footprints if
you had the dimensions readily available. Schmatic symbols are a
different thing because each schematic package has its own quirks
about how they are made I think.
FreePCB does not include schematics at all. Many people use TinyCAD
for that, but since layout is not closely tied to schematic capture,
it doesn't matter a lot what you use.
Rick
Curt Johnson
> Err, but a random-deleted net is actually easy to find, as you usually
> have more than one copy (as in, in the SCH, or even in a copy of the
> PCB ) ?
>
> Which Mentor flows/versions are you using ?
If I have plots from an earlier revision, I compare them with the new
revision one page at a time on a light box. Every difference has to be
traced to ensure that it is an intended change.
On a 10 layer PCB with 4 BGAs, about a dozen smaller packages and a
couple of hundred discretes, it takes me two or three days.
Not difficult, but extremely tedious.
Viewdraw & Pads. I'm using Viewdraw (or DxDesigner I think they call it
now) version 2006.1. I havn't been able to get the 2007 release to read
in any of our current projects.
The random net deleting feature has been in place since before I started
here in 1993; but before BGAs, we could always rework the boards.
Curt
Steve Ravet
xilinx flow manager. It takes a text file which has all the options for all
the backend tools, runs the tools in order, checking the status of the
previous step before running the next step. It's similar to a makefile flow
but more flexible I'd say.
Outside of some vendor training classes I've never actually run the ISE gui.
I do however use the synplify GUI, both for synthesis and to drive P&R.
That's how I found out about xflow.
--steve
"Oscar Almer" <o.a...@gmail.com> wrote in message
news:20091106130119.19849884@hummingbird...
:
: I, at least, gave up on the ise wrapper about a year and a half ago -
:
Oscar Almer
"Steve Ravet" <steve...@arm.com> wrote:
> If you're using makefiles, you might want to investigate xflow, which
> is the xilinx flow manager. It takes a text file which has all the
> options for all the backend tools, runs the tools in order, checking
> the status of the previous step before running the next step. It's
> similar to a makefile flow but more flexible I'd say.
>
> Outside of some vendor training classes I've never actually run the
> ISE gui.
>
From your description, the other thread on here, and a quick read on
Xilinx's site, it seems like it's a bit of a domain-specific
reimplementation of make with particular quirks. I suppose the upside
is that it's supported under windows as well, where you don't usually
get make without a bit of effort.
I am somewhat surprised about the assertion that it's more flexible
than make, as the entire point of make is to be as generic and
flexible as possible.
Thanks for pointing it out, as I was previously unaware of it, and it
might come in handy one day.
//Oscar
-jg
> malcolm wrote:
> > Err, but a random-deleted net is actually easy to find, as you usually
> > have more than one copy (as in, in the SCH, or even in a copy of the
> > PCB ) ?
>
> > Which Mentor flows/versions are you using ?
>
> If I have plots from an earlier revision, I compare them with the new
> revision one page at a time on a light box. Every difference has to be
> traced to ensure that it is an intended change.
>
> On a 10 layer PCB with 4 BGAs, about a dozen smaller packages and a
> couple of hundred discretes, it takes me two or three days.
>
> Not difficult, but extremely tedious.
yes, that I can believe...
However, PADS does allow an ASCII compare, which will do that
comparison in seconds ?.
You can also safely re-import a netlist at any time,
and it simply skips existing pin pairs, and will add any missing ones,
which will stand out as unrouted.
ASCII export/import also checks your database integrity, as it
rebuilds the design. DXF does the same.
You can also generate reports that count pin pairs/nets etc..
Or, if you want a more modern lightbox, we use GerbView:
http://www.softwarecompanions.com/gbupdate.html
This will export layered PDFs, and import multiple gerbers, and is is
low cost. Works well with PADS.
>
> Viewdraw & Pads. I'm using Viewdraw (or DxDesigner I think they call it
> now) version 2006.1. I havn't been able to get the 2007 release to read
> in any of our current projects.
>
> The random net deleting feature has been in place since before I started
> here in 1993; but before BGAs, we could always rework the boards.
Is it Viewdraw, or Pads that drops the info ?
Is this a whole net, or a pin-pair ?
-jg
Curt Johnson
>
> You can also generate reports that count pin pairs/nets etc..
That's an excellent idea. Matching net reports across revisions might
save some time. Thank you.
> You can also safely re-import a netlist at any time,
> and it simply skips existing pin pairs, and will add any missing ones,
> which will stand out as unrouted.
>
> Is it Viewdraw, or Pads that drops the info ?
> Is this a whole net, or a pin-pair ?
>
Re-importing the netlist seems to be the issue.
Entire nets disappear and the previously routed tracks are ripped up and
discarded. I can't say for sure that there is no indication that
anything is wrong, since another engineer is responsible for the PADS
side, but if there is, it isn't obvious enough for her, nor her
predecessors, to notice.
Curt
Steve Ravet
although it is simpler than make. I meant to say it is more flexible than a
batch file implementation.
--steve
"Oscar Almer" <o.almer@gmail..com> wrote in message
news:20091111111327.632100c8@hummingbird...
-jg
The humble netlist is a very good audit-check, and the supposedly
smarter direct linkages may be quicker, but they can also sometimes be
riskier....
So, if the changes are simple, I'd suggest using net-import-merge
(that does NOT rip up any traces, but it does need some manual
groundwork)
If the changes are more complex, then use direct-linkages, but
_follow_ that with a netlist import/compare check.
ie The old "trust, but verify" :)
-jg