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RTL View of synthezied code

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jozamm

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Dec 31, 2009, 2:28:27 AM12/31/09
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Hi all,

I implemented a small statemachine with 2 states, State A triggers
counter A, when counter A reaches 255 the state machine jumps to state
B which triggers counter B, when counter B reaches 255 the state
machine goes to state A again. This repeats forever.

The counter is implemented as a component and the top module
instantiates two of them. The code is in VHDL and I am using Xilinx
ISE 11.4 When I viewed the RTL schematic, one counter is connected to
the rest of the state machine and the counter is floating with no
connections. However when i wrote a testbench and simulated it the
result is correct.

Can please someone give me an explanation?

Thanks and Happy New Year,

Regards,

Joseph

jt_eaton

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Dec 31, 2009, 11:41:10 AM12/31/09
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It probably determined that the two counters are never used at the same
time and could use one to do both tasks. Try changing the time outs to
non-matching values and see how that affects the outcome.

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