Correlation Algorithm: converting user type integer array into std_logic_vector
iquadri
problem..
I have a complex correlation algorithm written in VHDL and the output
of this module is a user defined type
The top level of the correlation module is
COMPONENT MainApplication IS
PORT
(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
outMainappli : OUT TABLE_TYPE_1_Integerrange4096to4095);
END COMPONENT;
Where
TYPE TABLE_TYPE_1_Integerrange4096to4095 IS ARRAY(1 to 1) of Integer
range -4096 to 4095;
The application works fine and simulation produces the desired
result..
The problem arrives when i am trying to create a wrapper for this
module.. for certain reasons to interface the application with the OPB/
PLB buses, i want to convert my user defined integer array type into a
std_logic_vector..
I tried the following code in my adapter.vhd file, the adapter file
also has access to my userlibrary where the integer type is declared.
SIGNAL Tempresult1 : TABLE_TYPE_1_Integerrange4096to4095;
SIGNAL SignalConcat1 : STD_LOGIC_VECTOR (12 downto 0);
OMPONENT MainApplication IS
PORT
(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
outMainappli : OUT TABLE_TYPE_1_Integerrange4096to4095);
END COMPONENT;
begin
--USER logic
myapplication : MainApplication
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
--outMainappli => outtest
outMainappli => Tempresult1
);
toto : process(Bus2IP_Clk) is
begin
SignalConcat1 <= std_logic_vector(conv_signed((Tempresult1),13));
myport <= SignalConcat1;
end process toto;
I get the following errors :
ERROR:HDLParsers:808 - "C:/QDev/FIRFilterPDR/edk_ip/MyProcessorIPLib/
pcores/firfilter_v1_01_a/hdl/vhdl/user_logic.vhd" Line 176.
conv_signed can not have such operands in this context.
I know that this is a syntax error.. i tried to change the code, but
then i got the same error..
I really need help for this .. my work is being blocked due to this..
and no, i cannot change the output type of my application..
Any help will be greatly appreciated..
Jonathan Bromley
> begin
> SignalConcat1 <= std_logic_vector(conv_signed((Tempresult1),13));
> myport <= SignalConcat1;
> end process toto;
>
>
>I get the following errors :
>
>ERROR:HDLParsers:808 - "C:/QDev/FIRFilterPDR/edk_ip/MyProcessorIPLib/
>pcores/firfilter_v1_01_a/hdl/vhdl/user_logic.vhd" Line 176.
>conv_signed can not have such operands in this context.
Well, it looks more-or-less OK... You haven't told us
the one really important piece of information: which
packages did you "use" at the top of this entity?
A typical problem might be that you have
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
and so you have conflicting definitions of conv_signed?
It would be easier if you try to be A Good Person (tm):
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...
SignalConcat1 <= std_logic_vector(to_signed((Tempresult1),13));
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan...@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Brian Drummond
<jonathan...@MYCOMPANY.com> wrote:
>On Sat, 13 Jun 2009 07:57:42 -0700 (PDT), iquadri wrote:
>>ERROR:HDLParsers:808 - "C:/QDev/FIRFilterPDR/edk_ip/MyProcessorIPLib/
>>pcores/firfilter_v1_01_a/hdl/vhdl/user_logic.vhd" Line 176.
>>conv_signed can not have such operands in this context.
>
>Well, it looks more-or-less OK... You haven't told us
>the one really important piece of information: which
>packages did you "use" at the top of this entity?
>A typical problem might be that you have
>
> use ieee.std_logic_signed.all;
> use ieee.std_logic_arith.all;
>
>and so you have conflicting definitions of conv_signed?
>
>It would be easier if you try to be A Good Person (tm):
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
> ...
> SignalConcat1 <= std_logic_vector(to_signed((Tempresult1),13));
Definitely the best library and the best approach, but given the declarations
TYPE TABLE_TYPE_1_Integerrange4096to4095 IS ARRAY(1 to 1) of Integer
range -4096 to 4095;
and
SIGNAL Tempresult1 : TABLE_TYPE_1_Integerrange4096to4095;
SIGNAL SignalConcat1 : STD_LOGIC_VECTOR (12 downto 0);
don't you need to extract the integer from the single element array?
SignalConcat1 <= std_logic_vector(to_signed((Tempresult1(1)),13));
Incidentally, even though I'm a big fan of strong typing, I don't like this type
name strategy; it just adds clutter as well as being incredibly fragile; if you
later decide you need another bit of resolution you have a maintenance
nightmare.
What is the real intent of this (array containing a single)13 bit signed
integer? e.g. if it is the right resolution for your raw input data, then
TYPE Raw_Data IS Integer range -4096 to 4095;
TYPE Raw_Data_Table IS ARRAY(1 to 1) of Raw_Data;
might be more suitable.
Or since you need a matching STD_LOGIC_VECTOR...
subtype Raw_Word is STD_LOGIC_VECTOR (12 downto 0);
TYPE Raw_Data IS Integer range (-2**Raw_Word'high) to (2**Raw_Word'high - 1);
TYPE Raw_Data_Table IS ARRAY(1 to 1) of Raw_Data;
...
SIGNAL SignalConcat1 : Raw_Word;
SignalConcat1 <= std_logic_vector(to_signed((Tempresult1(1)),Raw_Word'length));
Now you can see at a glance what the intent of a signal is: raw data, processed
but unrounded; processed and rounded etc, rather than having to translate back
from integer ranges to design intent.
And if your next board has a 14-bit ADC you only need to change the type
declaration (especially after appropriate use of 'length as above); you don't
have to edit every usage of it - or worse - live with misleading names which no
longer reflect the actual data size!
You may also consider using numeric_std.signed instead of both Integer and
STD_LOGIC_VECTOR in this example; then the type conversions disappear. They may
pop up elsewhere; but if you are _using_ the type system instead of fighting it,
they will be few and far between. Mixing Integer and Signed (or subtypes of
these) is pretty painless, and Integer is usually faster in simulation. (You may
need to constrain its range, as you did, for fast compact synthesis results)
- Brian
Jonathan Bromley
>don't you need to extract the integer from the single element array?
>
>SignalConcat1 <= std_logic_vector(to_signed((Tempresult1(1)),13));
duh, yes. Too much haste AGAIN, sorry.
<hangs head in shame>
iquadri
wrote:
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
Thanks guys, it worked ..