Heck, we weren't even supplied with VirtexII Pro data books, I had to
ask for one from our rep.
During the IBM "technical training" track I actually got angry. At
least 90% of the presentation was IBM marketing, describing various
IBM PowerPC processors and cores. Now I can't remember which features
are in the core that is actually used in the PowerPC, since we were
bombarded with features spanning the entire IBM product line.
The keynote speakers talked about stuff that had nothing to do with
the VirtexII Pro, except in abstraction.
Apparently, this seminar was not targeted at engineers. I'll keep
that in mind the next time I get an invite to a Xilinx seminar.
*Microsym* Computers Inc.
Within Xilinx, I am known to be the harshest critic of marketing BS in public
seminars, and I have ( successfully?) fought for more and more technical "meat".
Originally, I had been concerned about PW2002, therefore I attended in San
Jose. And I came away excited, happy, and even proud.
The world has changed since the late 'eighties. Then we were a little-known
company, and had to tell the audience about all those neat features, from LUTs
and carry chains through LUT-RAMs and SRL16s, to the on-chip termination
resistors, and about many generations of software fixes and improvements.
Now, there are many new avenues to transmit information, from CDs to the Web, to
this newsgroup. We are already known and respected in the engineering community,
and most designers know that we have great features, usually better thought-out
than those of the competition.
Having won the attention, and perhaps even the hearts and minds of most design
engineers, we now face a new challenge: We have to convince engineering and
corporate management to change their mindset, to adopt multi-gigabit
transceivers and on-chip PowerPC for their next-generation designs. Or to give
up on ASICs. And in the larger companies, such decisions are usually not made at
the design engineer's level. So we have to sell our capabilities higher up the
FPGAs are not glue-logic anymore, they are now part of high-impact
architectural, system-level, and business decisions. So we have to change the
tone of our story, to appeal to a new audience.
We still have lots of detailed technical info, app notes, cores, books and CDs
and also training sessions and FAEs, ready to explore the finer details; and
many of these details are really utilized by the software automatically.
So, please, keep coming to our Seminars and Events, but also use all the other
ways to inform yourself about Xilinx products and solutions. The era of FPGAs
has just begun...
BTW, we just finished a great quarter, increasing our sales 20%
quarter-to-quarter, thanks to satisfied customers, like the ones in this
newsgroup. We weathered the storm without any lay-offs, just with
belt-tightening. That's something to be proud of, and thankful to you, our
Greg Neff wrote:
> Yesterday I attended PW2002 in Toronto. I have attended Xilinx
> promotional seminars since the days of the XC2000. Until now, I have
> found that the Xilinx seminars provided enough technical information
> to make the marketing content tolerable. PW2002 was a radical shift
> toward marketing glitz, at the expense of useful technical content.
>Within Xilinx, I am known to be the harshest critic of marketing BS in public
>seminars, and I have ( successfully?) fought for more and more technical "meat".
>Originally, I had been concerned about PW2002, therefore I attended in San
>Jose. And I came away excited, happy, and even proud.
In San Jose you could pick and choose which technical training tracks
to attend. In Toronto we were shown four preselected videos. The
rational for this is obvious, but it results in my experience being
much different than your experience.
Also, you have to put yourself in the shoes of an engineer that has
little or no knowledge of VirtexII Pro. If you were in this position,
how much would you have learned at PW2002? If you have not yet seen
the IBM (C1) track then I suggest you do. I think you will appreciate
my frustration with this presentation.
>Having won the attention, and perhaps even the hearts and minds of most design
>engineers, we now face a new challenge: We have to convince engineering and
>corporate management to change their mindset, to adopt multi-gigabit
>transceivers and on-chip PowerPC for their next-generation designs. Or to give
>up on ASICs. And in the larger companies, such decisions are usually not made at
>the design engineer's level. So we have to sell our capabilities higher up the
>FPGAs are not glue-logic anymore, they are now part of high-impact
>architectural, system-level, and business decisions. So we have to change the
>tone of our story, to appeal to a new audience.
As I said, it was clear that the target has shifted away from the
engineer. If that's what Xilinx wants to do then that's fine, but
this reduces the value of the presentation to me, since I am concerned
with the technical aspects. Since Xilinx listed engineers in the "who
should attend" list, I expected the same level of technical content as
was in previous seminars.
>We still have lots of detailed technical info, app notes, cores, books and CDs
>and also training sessions and FAEs, ready to explore the finer details; and
>many of these details are really utilized by the software automatically.
I agree whole-heartedly. My issue here is only with PW2002.
>So, please, keep coming to our Seminars and Events, but also use all the other
>ways to inform yourself about Xilinx products and solutions. The era of FPGAs
>has just begun...
Maybe Xilinx needs to have two different seminars. Something like
PW2002 for managers, and then in-depth technical presentations for
>BTW, we just finished a great quarter, increasing our sales 20%
>quarter-to-quarter, thanks to satisfied customers, like the ones in this
>newsgroup. We weathered the storm without any lay-offs, just with
>belt-tightening. That's something to be proud of, and thankful to you, our
I have always liked Xilinx technology, and I have no desire to change.
Xilinx competitors are always knocking on our door, and we always turn
PW2002 rubbed me the wrong way, and I heard other attendees grumble as
well. Xilinx should know this, and that's why I posted my review.
Thank you for your honest comments.
Anyone else out there wish to provide us with some feedback? Too techie? Too
marketing? To Rah Rah Rah?
Just because some of us are wildly excited doesn't mean that others are. I
understand that. In fact, since I have been working on Virtex II Pro for more than a
year now (old news for me), I was a more than a little suprised by the numbers
attending, and the success of the event. In retrospect, I realize the revolutionary
product that it is, and I am exciting about its future.
Remote locations vs. the main sites? We reached ~ 10,000 people, and I have to
believe some of them are on this newsgroup.
If you feel that you do not want your comments in the public eye, I will respect
that, and you can send them to Peter or myself directly.
We are likely to do this again, and we strive to always be improving.
> Anyone else out there wish to provide us with some feedback? Too techie? Too
> marketing? To Rah Rah Rah?
I found it to be a complete waste of time and will never again attend one of
these "seminars". I sat next to a Xilinx FAE who laughed and joked about the
hokiness of the whole thing making it impossible to even hear what was being
said, not that anything was worth hearing.
If this was for managers, why didn't you invite them? I'm not a manager,
why was I invited?
As my boss said, the way to learn about new Xilinx products is invite *them*
to come to *us* and present exactly what we want to know. So I already
knew way more about Virtex 2 Pro than was presented at this seminar
because we'd had it presented to us.
The fact that one had no choice (at the outlying locations) to pick which
sessions to view was NOT mentioned at all. I only discovered it while
looking through the brochure during one of those silly "Good Morning
America" type episodes. This was what angered me the most.
I assure you that many many people came away with a bad taste in their
mouths on this one.
> Remote locations vs. the main sites? We reached ~ 10,000 people,
> and I have to believe some of them are on this newsgroup.
No use for either Colorado Springs or the UK. Still, it does
not sound as if much was missed. Now if X only had the consultants'
briefings of old...
BTW, could you pls post a pointer to a recent X paper on power
dissipation in VirtexII. I saw a mention of it in EETimes around
a month ago. The conclusion was along the lines of 'routing burns
more than logic'
I as well did not find the presentations technical enough, luckily you guys
have another event coming up next month that promises to be more technical
(Xfest). I will definitely attend this.
Regardless, I had a fun time at the event and came away convinced that FPGAs
are the way to go for systems design.
My favorite speaker of the day was Howard Charney from Cisco, his speech
made me very excited about what I do for a living. He was a very powerful
I am looking forward to designing with the Virtex-II Pro.
> During the IBM "technical training" track I actually got angry. At
> least 90% of the presentation was IBM marketing, describing various
> IBM PowerPC processors and cores ...(snip>... we were
> bombarded with features spanning the entire IBM product line.
Same feeling here. I seemed like this session presented a migration
path for Virtex II Pros into IBM ASICs: same wafer technology, same
process, bus/macros from the same foundry... Easier that easypath?
But I was expecting the marketing hipe. I attended to be able to
understand some of the expectations designers might have after it. To
provided better support to them. With that in mind, I was glad I went.
I don't recall the article, I'll go look...
To help in the hunt, here is the reference to the eetimes
Quoting from eetimes:
Despite this reluctance to tackle the issue head-on, power consumption
could soon be at the top of the to-do list in the near future,
especially if programmable logic device (PLD) makers are serious
about winning sockets in power-sensitive consumer electronics
applications, said Xilinx's Trimberger.
Xilinx has already taken the first steps to raise the awareness of
power issues by disclosing a study on the hot spots in its latest
Virtex 2 architecture. In the paper, the company showed that 60
percent of the power consumption in the Virtex 2 family is from
routing while logic and clocking account for 16 and 14 percent,
Additionally, Xilinx found that the cluster of LUTs, flip-flops and
other circuitry that make up its configurable-logic blocks take up
5.9 microwatts per MHz for a typical design. But this is just for
"typical" designs; actual power consumption within the configurable
logic blocks (CLBs) can change wildly depending on the switching
activity. This can occur frequently in synchronous circuits, where
the inputs to the LUTs come in at different times during the same
clock cycle. This "glitching" effect could contribute up to 70 percent
of the power dissipation in a CMOS circuit, whether it's an ASIC or
I guess you feel an application note coming on :-)
"Austin Lesea" <austin...@xilinx.com> wrote in message
I wondered why I was writing this note about power... (actually I am).
In Virtex II and Virtex II Pro we see the beginnings of something that we
need to address with design techniques, tools, and automated software
awareness. If you can't do it manually, then there is no way to automate
it. Techniques to reduce the 'glitch' power Steve mentions includes
reducing the amout of interconnect attached to a toggling LUT node (ie
register in the CLB), or registering ahead of the inputs to reduce the
skew int he arrival times at the LUT to reduce gratuitous toggling.
I imagine someday a button labled "optimize for power" in the FPGA
synthesis flow, just as there are area vs speed buttons today.
Right now, there is no "hot spot" as the silicon conducts the heat
sufficiently well. The hot spots Steve is referring to are spots which a
perhaps a few degrees C warmer than the surrounding areas. Easily imaged
with IR sensors.
Steve is right, and when he says "could be" he is just teasing. We are
designing 'future' FPGAs already.
As for the routing contributing to power, we have definitely seen an effect.
Floorplanning seems to consistently decrease power by 20% or more over the
same design automatically placed.
We recently did our first design that needed fans on the FPGAs (we've got a
couple of designs with heatsinks). I had a picture of the board with pentium
style coolers on the V2000E's with my exhibit at FCCM earlier this week. In
that case, each FPGA is dissipating 14w (measured).
Austin Lesea wrote:
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759