Benchmark circuits - in VHDL for FPGA
cso...@dso.org.sg
Does anyone have recommendations to find benchmark circuits for
FPGA - preferrably in VHDL ?
Thanks in advance.
email: cso...@dso.org.sg
Wade D. Peterson
I've been thinking about this for sometime myself. Gate counts and speed are
two areas where it's hard to get *OBJECTIVE* data on FPGA devices.
The problem with benchmarks is that most circuits seem to specialize in certain
types of logic (gates, multiplexors, three-state buses, RAM, etc.). No matter
what you use, somebody will complain that it doesn't represent what they're
trying to benchmark. The same thing happens with computer benchmarks.
I was talking to guy from the Bank of Boston about this at the DAC conference in
New Orleans this month. They are also confused about FPGA gate counts and
speed. We've got an 8-bit RISC processor (VHDL IP Core) that will run on most
of the popular FPGA parts, and it occurs to me that would be an excellent
benchmark circuit because it has a large variety of circuits inside of it (RAM,
ROM, multiplexors, random logic, ALU, etc.). I suggested that the Bank of
Boston develop a benchmark to compare FPGA gate counts and speeds, and offered
him a core license to do that.
It occurs to me that the same approach would work to benchmark VHDL synthesis
tools too.
--
Wade D. Peterson
Silicore Corporation
3525 E. 27th St. No. 301, Minneapolis, MN USA 55406
TEL: (612) 722-3815, FAX: (612) 722-5841
URL: http://www.silicore.net/ E-MAIL: pete...@maroon.tc.umn.edu
Alasdair MacLean
Wade D. Peterson wrote in message <7m39ct$e0i$1...@news1.tc.umn.edu>...
><cso...@dso.org.sg> wrote in message news:3781BA...@dso.org.sg...
>> Hello,
>>
>> Does anyone have recommendations to find benchmark circuits for
>>
>> Thanks in advance.
>>
>> email: cso...@dso.org.sg
>
>I've been thinking about this for sometime myself. Gate counts and speed
are
>two areas where it's hard to get *OBJECTIVE* data on FPGA devices.
>
snip...
>
>--
>Wade D. Peterson
>Silicore Corporation
>3525 E. 27th St. No. 301, Minneapolis, MN USA 55406
>TEL: (612) 722-3815, FAX: (612) 722-5841
>URL: http://www.silicore.net/ E-MAIL: pete...@maroon.tc.umn.edu
>
>
>
There used to be an organisation by the name of PREP (PRogrammable
Electronics Performance Corporation) who published a set of benchmark
circuits for FPGAs in VHDL on their web pages at http://www.prep.org/ ,
however the company and the web page both now appear to be defunct.
Other contributors to the newsgroup will be able to fill in the details, but
I believe a combination of vendors trying to bend the rules to suit their
own marketing claims, combined with a lack of general acceptance eventually
lead to PREP's failure.
If you're interested, I have some of the benchmark circuits but if you want
details on how the tests were performed, try to get hold of a copy of
Actel's 1995 Data Book - it has a chapter devoted to the subject.
-- Alasdair
Alasdair MacLean, Senior Development Engineer,
Marconi Electronic Systems, Electro Optic Systems Division,
4 Ferry Road, Silverknowes, Edinburgh EH4 4AD
Telephone: 0131-343-5711, GNET: 709 5711
email: alasdair...@gecm.com
Herman Schmit
: > FPGA - preferrably in VHDL ?
: I've been thinking about this for sometime myself. Gate counts and speed are
: two areas where it's hard to get *OBJECTIVE* data on FPGA devices.
: The problem with benchmarks is that most circuits seem to specialize in certain
: types of logic (gates, multiplexors, three-state buses, RAM, etc.). No matter
: what you use, somebody will complain that it doesn't represent what they're
: trying to benchmark. The same thing happens with computer
: benchmarks.
This is a problem across the board in CAD. For that reason, we've
been working to improve the status of benchmark circuits that are
available to researchers and customers. We currently have a
"vertical" benchmark available on our web page. It is a 24-bit DSP
with memories, multipliers, control, big adders, and all sorts of
other structures. I believe that it really pushes ASIC Synthesis and
P&R tools. It should also push FPGA tools, but we haven't yet tried
it.
I think the distinction with our benchmark is that we give away lots
of different representations (RTL, gate-level, switch-level, and
geometry). This allows you to test your flow from any starting
point. In addition, we have a fairly extensive functional testbench.
All of this can be found by following the "benchmarks" link from:
(The current URL will be updated soon, so please bookmark the CEDA
site only.)
Please let us know if you have any questions, or just let us know that
you're using this productively. We'll be putting a number of other
designs on this site in the coming year, including an ARM-like core, a
programmable FIR filter, and a picoJava processor.
(BTW, Sun is now releasing their picoJava and SPARC cores under a
license that allows you to use them for benchmarking. Might also be
useful to you.)
Herman
------------------------------------------------
Herman Schmit, Ph.D., Assistant Professor
Department of Electrical and Computer Engineering
Carnegie Mellon University
5000 Forbes Ave., Pittsburgh PA 15213
Tel: (412) 268-6470 FAX: (412) 268-3204
email: her...@ece.cmu.edu