Disabled generate gives compile error in Modelsim

[Stef]

[This is a repost. Posted this to comp.lang.vhdl a few days ago, but no
replies. So maybe nobody knows the answer, it was a malformed question
or there are no readers in that group. So a repost (with a little
clarification, I hope) with the comp.arch.fpga added at least resolves
the last option. ;-)]


It has been a while since I used VHDL so I am a little rusty. Did not
much use the generate statement in the past either. And now I have the
problem that I have (been given) a VHDL model that has a conditional
generate in it. And this does not work as I expected. In the model, the
purpose of the conditional is that there is a clock source that cannot be
simulated, so an alternative is simulated. I have reproduced the problem
in the minimal example below.

If I declare 'sigio' as 'inout', as below and as I got the model, then when
I simulate it, the signals in the simulation remain 'U'. So somehow the
'gentest' model drives the 'sigio' signal although the generic
'this_is_a_simulation' has been set to true.

If I declare 'sigio' as 'in' (change the comment line in the port), I get a
compilation error in Modelsim on driving the type 'in' 'sigio' signal. When
I then just comment out the 'rtlblk' generate, the model simulates as
expected.

Can this be made to work as expected (simulation/clocksource model switch
without changing the code)? Unfortunately I cannot get information from the
original creator of this construct and I don't know if it ever worked.


-------- gentest.vhd ------------
library ieee;
use ieee.std_logic_1164.all;

entity gentest is
generic(
this_is_a_simulation : boolean := true
);
port(
-- sigio : in std_logic; -- Compile error
sigio : inout std_logic; -- Original line
sigout : out std_logic
);
end entity gentest;

architecture behav of gentest is
begin

-- If I comment out this generate, the compile error with sigio as
-- 'in' disappears.
-- But should this section not be ignored if 'this_is_a_simulation'
-- is set to false?
rtlblk : if this_is_a_simulation = false generate
sigio <= '1';
sigout <= '1';
end generate;

simblk : if this_is_a_simulation = true generate
sigout <= sigio;
end generate;

end architecture behav;


-------- tb_gentest.vhd ------------
library ieee;
use ieee.std_logic_1164.all;

entity tb_gentest is
end entity tb_gentest;

architecture behav of tb_gentest is
signal clk : std_logic;
signal sigout : std_logic;
begin

gentest_inst : entity work.gentest
generic map(
this_is_a_simulation => true
)
port map(
sigio => clk,
sigout => sigout
);

process
begin
clk <= '0';
wait for 10ns;
clk <= '1';
wait for 10ns;
end process;

end architecture behav;


--
Stef

The world is no nursery.
- Sigmund Freud

[KJ]

On Friday, December 9, 2022 at 6:20:15 AM UTC-5, Stef wrote:
> [This is a repost. Posted this to comp.lang.vhdl a few days ago, but no
> replies. So maybe nobody knows the answer, it was a malformed question

There is a reply now in comp.lang.vhdl

Kevin Jennings