how to use ram or memory
The Lord of War
i was wondering how do i use the onboard sram, i need to create a big
memory structure so do i just do:
type dataout is array (0 to 1048576) of std_logic_vector(15 downto 0);
signal mem_struct : dataout;
and the fpga knows what to do and where to save the stuff and then use
mem_struct as my memory structure or is there a way (a procedure) to use
the onboard sram or flash for what matters.
i hope i'm clear enough
if it helps i am using virtex 4 xc4vfx20 and xilinx ise 9.2, and i have
512M scan disk flash and SRAM module (ZBT Synchronous SRAM) on the board
itself
thanks in advance
regards
The Lord of War
MikeWhy
news:arGdnTDYRLmL69DX...@giganews.com...
Me personally, I find (1024 * 1024 - 1) more easily readable for intent, and
small mistakes harder to miss. As to your question, simply: No, but it can
be "taught". The beauty of a blank canvas is it doesn't presume to know the
brush's intent.
The Lord of War
do some fancy stuff and calls to be able to use them? and if so what do i
need to do?
thanks
Enes Erdin
You have to observe the datasheet of the SRAM, the input output timing
diagram, the connections between the SRAM and the FPGA. The array
solution is not a logical solution since by creating an array you can
not reach to the SRAM it only tries to create a memory inside the FPGA
which will not be synthesizable.
MikeWhy
> eh no for what no for I cant use the sram that is onboard or no I have to
> do some fancy stuff and calls to be able to use them? and if so what do i
> need to do?
No, the fpga doesn't of itself know about the board. It doesn't know about
the devices on the board. And it doesn't know the minutiae of operation of
the devices on the board.
As to what to do, it depends on what you're trying to do. An embedded system
can use the Xilinx EDK to interface with the device, attach it to the
peripheral bus, assign it room in the memory space, and build drivers to
access and control the device from software. For a hardware only solution,
start with the device's datasheet, and build the interface circuitry in the
fpga. The "process" you can "call" to work with the device might already
exist. They're more generally referred to as IP Cores. I expect you'll find
the required IP Cores in the Xilinx tools.
"Fancy stuff" on the fpga is more properly thought of as describing and
connecting circuitry. It is not software "calls" using a strange new
programming language. I hope you'll find that distinction helpful.
The Lord of War
I dont know but maybe (or definitely) you guys are way more advanced than
me that's why I'm getting nothing, so to be clear I have an fpga board on
it is the virtex 4 and lots of other chips including an sram module and a
flash (scan disk) and something called linear flash all this is on the SAME
board as the FPGA and what I'm trying to do is to use these modules to save
information temporarily, so I need to save data in the sram (the one
ONboard) to be able to use later. I'm using VHDL to code my project, and my
question is; HOW can I use these resources which are on the same board.
please help the declaring big array did not work.
any tutorials or sample code is greatly appreciated
thanks a lot guys and best of regards
Dave P
Declaring an array in VHDL uses memory _inside_ the FPGA. You need to use
memory _outside_ the FPGA. Imagine that the SRAM chip is connected to a
microprocessor, instead of a FPGA. The micro and the SRAM chip communicate
via Address lines, Data lines (I/O) and control lines (cs*, we*, rd, wr,
etc). The micro puts out a valid address, and sets the control lines to
read from or write to the SRAM chip. The data travels on the data lines
(bus). So, the FPGA needs to do something similar; this is called a memory
controller. The timing of the memory controller must match the specs of
the SRAM chip. There may be existing IP for Virtex that already does this.
Perhaps Xilinx's CoreGen creates one (look in ISE). Your VHDL "code" then
uses the memory controller to communicate with the SRAM.
HTH
-Dave Pollum
MikeWhy
It sounds like the ML405 board. www.xilinx.com is where I would look first
for sample code and tutorials. You'll find there as many application notes
and documents as you would care to read. The memory manufacturers' websites
will also have vitally useful information.
With that said, I think it's way too much all at once to tackle as a first
effort. If you care to, back up a few steps, tell us what you're doing and
why, and what your expectations are. If it's a school project, stick with
their program, of course. But, if you're on your own, maybe someone here can
suggest a more reasonable progression to get you rolling. It won't be a
short journey, but you might find it more satisfying and worthwhile than
immediate gratification on your near term goal.
The Lord of War
save is in digital form in some kind of buffer (here comes the sram role)
and then read it back after some time and convert it back to analog, thus
producing a delay that can be controlled. and I need to do long delays so I
nee a big buffer or memory. I checked the xilinx website there is no
mention on the use of the onboard ram, so if any one have a lead on the
subject please help, I need to know HOW to do this, a tutorial is good too.
I'll keep searching and I'll post if I find anything new.
regards
rickman
Maybe I missed something, but what board are you using? Are you
asking for help with the board you have or ZBT ram in general, or are
you asking for help with the HDL? Or maybe all three?
Rick
The Lord of War
>> Sadly I'm on my own, and what I'm trying to do is sample an analog
signal
>> save is in digital form in some kind of buffer (here comes the sram
role)
>> and then read it back after some time and convert it back to analog,
thus
>> producing a delay that can be controlled. and I need to do long delays
> I
>> nee a big buffer or memory. I checked the xilinx website there is no
>> mention on the use of the onboard ram, so if any one have a lead on
the
>> subject please help, I need to know HOW to do this, a tutorial is good
>o.
>> I'll keep searching and I'll post if I find anything new.
>>
>> regards
>
>Maybe I missed something, but what board are you using? Are you
>asking for help with the board you have or ZBT ram in general, or are
>you asking for help with the HDL? Or maybe all three?
>
>Rick
>
i'm using virtex 4 board 405/6 and on the board is a sram chip and it is
ZBT, this sram is on the same board so I need not wire any external
circuit since the sram module is on the same board, I'm coding using VHDL
and all I need to know is HOW can I use this sram module -which is on the
same board :). so HOW e.g. a function call or a built in library with some
entity that uses the onboard ram or how can I access this ram?? (what do i
need to do)
thanks in advance
MikeWhy
The help we give can only be as specific as the information you give us. We
don't know the sample rate from your ADC; we don't know anything about your
board; we don't know anything about the synchronous RAM on your board.
Research this:
Find the documentation for your board. Identify the memory device you are
trying to read and write. Make note of what signals connect to the fpga.
Identify the pins on the fpga that connect to the memory device.
Find the documentation for the memory device. Make note of the functions of
the signals connected to the fpga. Make note of the timing information.
You will program the fpga to generate the signals to read and write the
device. Begin forming in your mind the operations the fpga must perform to
do this.
You will read and write one or possibly more data words on each ADC sample.
How many bits in a data sample? How many bits in a memory data word? Does
the data sample fit in a memory word? Does the sample rate leave enough time
to read one sample and write a new sample on each cycle?
A ring buffer is suitable for use as a delay line. Define the delay time in
terms of sample time. For each sample, read the old sample value, and
overwrite it with the new sample. Advance to the next memory location. A
modulo-N counter can be used to drive the memory address lines. It counts up
to N-1 and then starts over at 0.
The memory device has a number of control lines. What are their functions?
What signals will you drive to read a memory location? What signals will you
drive to write a memory location?
The ADC sample rate will almost certainly be different from this circuit's
clock rate. How will you signal the start of a sample period?
Since you didn't ask about the ADC or DAC, I presume you have this part
under control. The memory is only moderately more complex than reading and
writing those other devices.
You will also need a one time reset to initialize the ring buffer contents
to an unobnoxious value. Alternatively, consider just not sending the
garbage values read during the first delay cycle.
I would go about building things in this order:
Write the HDL for the modulo-N counter. Simulate and verify its operation.
Add the memory control lines. Add this to the simulation and verify its
operation.
Write a testbench to generate data samples and simulate the memory device.
Verify the module's operation in the simulator.
Wire the module to your (presumably) already working ADC and DAC modules.
Good luck.
MikeWhy
Google on "zbt sram", among the first few hits:
http://www.xilinx.com/support/documentation/application_notes/xapp136.pdf
Also for the same search:
http://www.opencores.org/?do=project&who=zbt_sram_controller
The Lord of War
new stuff.