Altera Cyclone low-cost FPGA chips?

5 views
Skip to first unread message

cheponis

unread,
Sep 23, 2002, 6:25:05 AM9/23/02
to
Hi, does anyone here have any info on the new Altera "cyclone"
inexpensive chips?

The only reference I've seen is
http://www.bayarea.com/mld/mercurynews/business/4133199.htm

Thanks.

ds

unread,
Sep 23, 2002, 9:49:13 AM9/23/02
to

rickman

unread,
Sep 23, 2002, 10:04:57 AM9/23/02
to
You will find the Altera press release here

http://www.altera.com/corporate/news_room/releases/products/nr-cyclone.html?xy=whp1_cycpr


Or you can start on the reading about the details here

http://www.altera.com/products/devices/cyclone/cyc-index.jsp

Looks like they are finally responding to Spartan. This can only be
good for the users.

--

Rick "rickman" Collins

rick.c...@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

rickman

unread,
Sep 23, 2002, 10:55:14 AM9/23/02
to
rickman wrote:
>
> You will find the Altera press release here
>
> http://www.altera.com/corporate/news_room/releases/products/nr-cyclone.html?xy=whp1_cycpr
>
> Or you can start on the reading about the details here
>
> http://www.altera.com/products/devices/cyclone/cyc-index.jsp
>
> Looks like they are finally responding to Spartan. This can only be
> good for the users.

After taking a quick look at the Cyclone family, I can see they are
taking a slightly different approach than Xilinx.

The Xilinx Spartan II series is based on the Virtex family just as the
Spartan was based on the XC4000. In contrast, it looks like the Cyclone
family is not directly based on any existing Altera family.

Comparing the Spartan II to the Cyclone shows that the Cyclone has a
higher LUT to IO ratio. The Cyclone looks a little more like a
potential future Spartan III based on the Virtex II family which also
has a high LUT to IO ratio.

SpartanII 2S50E 2S100E 2S150E 2S200E 2S300E
LUTs 1536 2400 3456 4700 6144
IOs 182 202 263 289 329
ratio 8 12 13 16 19

Cyclone EP1C3 EP1C6 EP1C12 EP1C20
LUTs 2910 5980 12060 20060
IOs 104 185 249 301
ratio 28 32 48 67

As it turns out this makes the Cyclone parts very expensive in high IO
count applications. Further, Altera seems to not have small chip scale
packages for the low end of the family. Looks like they really tried to
go for a low price, limited options product line, even more so than the
Spartan II. The high LUT count may prove a benefit for some
applications though.

Jack

unread,
Sep 23, 2002, 12:28:25 PM9/23/02
to
It's in EE Times as well. Looks pretty good. I found datasheets, app
notes, lots of other material linked through their press release.

http://www.altera.com/corporate/news_room/releases/products/nr-cyclone.html

Jack

Jan Gray

unread,
Sep 23, 2002, 1:04:25 PM9/23/02
to
I have started some Cyclone links and commentary at fpgacpu.org.

Jan Gray, Gray Research LLC

Marc Randolph

unread,
Sep 24, 2002, 12:34:47 PM9/24/02
to
rickman <spamgo...@yahoo.com> wrote in message news:<3D8F2B52...@yahoo.com>...

> After taking a quick look at the Cyclone family, I can see they are
> taking a slightly different approach than Xilinx.
>
> The Xilinx Spartan II series is based on the Virtex family just as the
> Spartan was based on the XC4000. In contrast, it looks like the Cyclone
> family is not directly based on any existing Altera family.
>
> Comparing the Spartan II to the Cyclone shows that the Cyclone has a
> higher LUT to IO ratio. The Cyclone looks a little more like a
> potential future Spartan III based on the Virtex II family which also
> has a high LUT to IO ratio.
>
> SpartanII 2S50E 2S100E 2S150E 2S200E 2S300E
> LUTs 1536 2400 3456 4700 6144
> IOs 182 202 263 289 329
> ratio 8 12 13 16 19
>
> Cyclone EP1C3 EP1C6 EP1C12 EP1C20
> LUTs 2910 5980 12060 20060
> IOs 104 185 249 301
> ratio 28 32 48 67
>
> As it turns out this makes the Cyclone parts very expensive in high IO
> count applications. Further, Altera seems to not have small chip scale
> packages for the low end of the family. Looks like they really tried to
> go for a low price, limited options product line, even more so than the
> Spartan II. The high LUT count may prove a benefit for some
> applications though.

From what I've seen, the last 3 or so generations of Altera devices
appear to have higher LUT/IO ratios than the comparible Xilinx family.
In general, at least in the telecom industry where I am, I think this
is the right direction to be moving and Xilinx appears to have finally
figured this out, from the looks of the proposed Spartan III.
Undoubtly, the problem is identifing exactly what features and what
packages to offer for given LUT ranges.

We are constantly bumping up against the largest device in a cost
effective package. IE, we definitely would move to using a larger
Virtex-II (XC2V4000) if it were available in anything smaller than an
expensive 1152 pin flip chip package [or the monster 40x40 1.27 mm BGA
package]. I realize Xilinx probably has their reasons for the
offerings they have (most likely thermal?), but if they could overcome
that, it'd be easy money for them, cause I'll bet there are others out
there in the same boat as us.

Same went for the Virtex-E... the 600E was the largest you could get
in a reasonable cost/size package. The XCV812EM was available, but
not competitively priced. We would have used a large device if Xilinx
had offered it in a FG676. Instead, in both the Virtex-II and
Virtex-E, we get to play roulette with MAP and PAR, constaintly
bumping up against random timing violations that differ from run to
run.

Anyone else in the same boat, wishing there were an XC2V4000-FG676 [or
actually, just a 3000 with more LUTs, not more BRAM's]?

Marc

Austin Lesea

unread,
Sep 24, 2002, 1:32:45 PM9/24/02
to
Marc,

I will reiterate something Peter has said once before:  Altera has announced that they will have (note use of the future tense) .......

So comparing an exisiting Spartan IIE product that is selling like crazy today (and is the fourth generation Spartan Product) with a product that doesn't exist yet at a future technology node is a little silly.

Also stating their projected future price per LUT is better than the existing price per LUT is silly.  Of course:  Moore's Law if they haven't totally missed the boat (which they are definitely smart enough not to do).

Virtex II Pro is the ninth generation FPGA product.

Maybe we have been doing this for awhile, and maybe we have figured out what sells, and what works?

Obviously, we can't please absolutely everyone.  I appreciate the comments, and we always listen to what the customer wants.

Austin

Xanatos

unread,
Sep 24, 2002, 6:15:32 PM9/24/02
to
They *will have* should scare you (Xilinx). Most people doubted that Altera could deliver Stratix, and they did....and it is a fantastic product. They will deliver with this line as well.
 
From what I can see (and I'm not referring to the useless online blurbs from Vice Presidents), this Cyclone product has lots of interest....and that makes sense, due to the price targets and the features in Cyclone.
 
Care to comment on the Xilinx Ships 40 Millionth Spartan Device - World's Lowest Cost FPGA P.R that same day? Reactive, I would say.
 
I'm not "attacking"....but I think we see that Altera has awakened the sleeping Giant (Xilinx), and it should make for some great new products coming out down the line!
 
-Xanatos 
 
 
"Austin Lesea" <austin...@xilinx.com> wrote in message news:3D90A1BD...@xilinx.com...

Austin Lesea

unread,
Sep 24, 2002, 6:49:00 PM9/24/02
to
Xanatos,

The market is a great thing.  Competition is wonderful.  Best products win.

As for 'scare', that is a strange reaction from an engineer.  Personally, I feel challenged to do each product even better than the last, regardless of what Altera is doing.  After all, Altera is not the customer.  In this market we compete with the ASIC and ASSP suppliers: it is pretty large market, larger than all other PLDs combined.  Altera's vision of the market is no less valid, and no more valid than ours.

40 million Spartan devices says it all:  we are already very successful in this market, and it is Altera that is reacting to our success.  To remind everyone that we were there first is just our way of balancing the marketing "useless blurbs" (your words, not mine).

Imitation is the sincerest form of flattery.  Now they want to immitate our success in the consumer space.  Welcome to telematics, game boxes, hand held devices, set top boxes, and displays (and who knows what else).  A whole different space from the line cards, servers, telecom and data switch world.

This is the world where the product sales pitch might be "Xilinx just sounds better" or "Xilinx makes the picture look better."  Talk about a scarey world.....

Austin

Tim

unread,
Sep 24, 2002, 2:24:30 PM9/24/02
to
Austin Lesea wrote

> Virtex II Pro is the ninth generation FPGA product.

Using a conventional interpretation of 'generation',
and omitting the in-between/nothing-much-new products:

2000
3000
4000/E
Virtex/E
VirtexII/Pro

Of course, if you include the 3000A, 4000A, 4000D,
4000H, 5200, 8200, and all the rest, it is probably
generation 42 :-)

BTW, was there ever silicon of a 1000 series, before
the 2064?

Peter Alfke

unread,
Sep 24, 2002, 7:44:51 PM9/24/02
to Tim

Tim wrote:

> BTW, was there ever silicon of a 1000 series, before
> the 2064?

No, 2064, (followed by 2018, then 3020...) was the first Xilinx FPGA.

Peter Alfke


Jim Granville

unread,
Sep 24, 2002, 8:08:50 PM9/24/02
to
Austin Lesea wrote:
>
> Marc,
>
> I will reiterate something Peter has said once before: Altera has
> announced that they will have (note use of the future tense) .......
>
> So comparing an exisiting Spartan IIE product that is selling like
> crazy today (and is the fourth generation Spartan Product) with a
> product that doesn't exist yet at a future technology node is a little
> silly.

Of course, but it is an almost universal marketing reflex.

Considering the technical skills of the customer base, and all the
credit given to 'listening to the customers', you would expect
semiconductor company press releases to read less
like soap powder adverts....

Digging about on Altera's releases, we can get a time-line
( now, they could have presented a time line, but you never see
that in SoapPowder 101 )


Cyclone time line:

Beta SW : Quartus II version 2.1, July 2002
Software Support : Now, Quartus II version 2.1 (service pack 1)
Programming : Programming file generation for Cyclone devices will
be supported
in a subsequent software release
Beta Samples : ??
Eng Samples : E.S. Cyclone EP1C20 and EP1C6 January and February
2003, respectively.
E.S EP1C3 and EP1C12 in April 2003.
Release : All family members will be in full production in the
first half of 2003.
Process : 1.5V, 0.13µm, all-layer-copper process from TSMC.

Clearly not in general release right now, but not 100% vaporware as
'a product that doesn't exist yet at a future technology node' suggests.
0.13u is not 'future technology', and they will have some silicon in
their
LABs. ( and probably at key customers )


Looking thru Altera's info, the configuration memory looked to have
taken
a significant step.


-jg

Marc Randolph

unread,
Sep 24, 2002, 10:38:28 PM9/24/02
to
Howdy Austin,

Austin Lesea <austin...@xilinx.com> wrote in message news:<3D90A1BD...@xilinx.com>...

> Marc,
>
> I will reiterate something Peter has said once before: Altera has announced
> that they will have (note use of the future tense) .......
>
> So comparing an exisiting Spartan IIE product that is selling like crazy
> today (and is the fourth generation Spartan Product) with a product that
> doesn't exist yet at a future technology node is a little silly.
>
> Also stating their projected future price per LUT is better than the existing
> price per LUT is silly. Of course: Moore's Law if they haven't totally
> missed the boat (which they are definitely smart enough not to do).

Howdy Austin,

Perhaps I didn't write my post clearly. I have no clue what Altera
will be charging per LUT, nor do I have any information on the devices
to compare them to Spartan IIE's - and I don't think I came close to
referencing either item in my post. I was simply using Rick's
observations as a spring-board to say that I think this direction
(higher LUT to I/O ratio) is overdue, and gave but two examples.

Truth be told, we ran into this on two XC2V3000 designs and at least
two, if not three XCV600E designs. An XC2V1000 design is nearly in
the same boat. The point I was trying to make was that if we (a very
small company) have run into this 4 or 5 times in the past 2 years, I
suspect there are alot more out there just like us.



> Virtex II Pro is the ninth generation FPGA product.

And it is quite an impressive product, as were previous families of
Xilinx parts when they arrived. It is truely a marvel that so much
can be done with such a small, cost effective device. The amazing
part is that even more could be done with them if some BRAM's were
traded for LUT's, thereby upping the LUT to I/O ratio! ;-)



> Maybe we have been doing this for awhile, and maybe we have figured out what
> sells, and what works?

Yes, overall I think you have. Sales of the Virtex-II are proving
this out. But be careful about repeating that too much. There are at
least two major telecom silicon vendors out there that fell into that
exact trap and are now without some key products. The president of
one of the companies (one you do business with, in fact) is irrate
with his product management staff over it.

> Obviously, we can't please absolutely everyone.

I agree, and would take it a step further: you almost don't want to
please everyone. If you do even think about trying to please
everyone, it means you are making too many compromises, which will
force the masses to pay for things they don't want or need. That
creates and opening for a competitor.

> I appreciate the comments,
> and we always listen to what the customer wants.

That is great to hear - both as an engineer and an investor.

Best regards,

Marc

Peter Alfke

unread,
Sep 24, 2002, 11:51:30 PM9/24/02
to
Marc, I talked with Austin about your previous posting (of this morning).
It is true that the Virtex families emphasize high I/O count, but that is driven by market
demand.
One of the few painless modifications we can make at any time to our product offerings is
device/package matching. Within reason and with some physical limitations, we can put "any die in
any package". The actual offered combinations really depend on demand from our dear customers.
Unfortunately, many have stayed away from the low-pin-count offerings that you like so much. And
yes "we listen to our customers". Too much or not enough?

Peter Alfke, Xilinx Applications

Nicholas C. Weaver

unread,
Sep 25, 2002, 12:09:48 AM9/25/02
to
In article <15881dde.02092...@posting.google.com>,

Marc Randolph <mr...@my-deja.com> wrote:
>And it is quite an impressive product, as were previous families of
>Xilinx parts when they arrived. It is truely a marvel that so much
>can be done with such a small, cost effective device. The amazing
>part is that even more could be done with them if some BRAM's were
>traded for LUT's, thereby upping the LUT to I/O ratio! ;-)

Actually, no. If you look at a Xilinx die, you realize that the
memory is a very small fraction. You can really see this on the
Virtex E die photo, the BlockRAMs are only about 2x the width of a CLB
column

http://www.xilinx.com/company/press/products/images/large/virtexedie.jpg


This is one of the reasons why progressive parts are more memory
heavy: it really is comparatively small, but when you want the memory,
you REALLY want the memory, making it high value.
--
Nicholas C. Weaver nwe...@cs.berkeley.edu

Phil Hays

unread,
Sep 25, 2002, 12:36:31 AM9/25/02
to
Marc Randolph wrote:

> The amazing
> part is that even more could be done with them if some BRAM's were
> traded for LUT's, thereby upping the LUT to I/O ratio! ;-)

Please, no. Especially in the larger parts, please more block RAM, not
less.

As parts get larger, and designs get faster, moderate sized internal
buffers have been and will continue to be very useful, at least for
designs I've done. Last big project I did used 100% of the block RAMS
and a bunch of LUTS as RAMS as well.

A key point is that FPGAs are used for lots of different sorts of
designs, and they can never be a close fit for all but a tiny subset of
these designs. There will always be some users asking for more A and
less B and other users asking for more B and less A. Some designs need
one clock tree, why are you wasting resources making more? Others need
5, or 8, or more. Some need more LUTS. Some will need more RAM. I
have no past, current or known future use for multipliers, yet I'd
suspect that a bunch of DSP guys would whine loudly if you took the
multipliers out.

The one thing I'd ask for is some programmable delays for a fraction of
the pins for a 90 degree phase shift for the DQS for DDR RAMS. About 1
in 4 IOBs or 1 in 8 IOBs would be just fine, thank you. Do the Altera
Cyclone parts have something like this?


--
Phil Hays

Message has been deleted

Jim Granville

unread,
Sep 25, 2002, 1:31:47 AM9/25/02
to

Package alone is not likely to be a dominant cost factor :
Far more relevent, will be die area, yield, testing times, FAB run
volumes,
( mask amortise) plus the M Squared fudge factor ( M^2 = Marketing
Margin )

( see also other thread on higher end CPLD price-kick )

That said, it makes sound sense to offer a broad range of die in
a common package - designs NEVER get smaller as they mature :)

A good example, that proves this can be done, is the Actel ProASIC
- they offer ALL die, from 75K to 1000K, in a PQFP208 package ( 7 steps
).

If you really need IO, they also have a FBGA1152 on the biggest device.

-jg

ds

unread,
Sep 25, 2002, 1:34:44 AM9/25/02
to
"Each Cyclone device is equipped to interface with DDR SDRAM and FCRAM
devices using optimized I/O pins as seen in Figure 1. Each I/O bank features
two sets of interface signal pins and each set contains a single data strobe
(DQS) pin and eight associated data (DQ) pins. These pins are designed for
high-speed data transfer with an external memory device using the SSTL-2
Class II I/O standard. Up to 48 DQ pins are available per device with 8
corresponding DQS pins, supporting a single dual-inline memory module (DIMM)
with 32-bit data and error correction."

http://www.altera.com/products/devices/cyclone/features/cyc-ext_mem_int.html

Should answer the question below.

> The one thing I'd ask for is some programmable delays for a fraction of
> the pins for a 90 degree phase shift for the DQS for DDR RAMS. About 1
> in 4 IOBs or 1 in 8 IOBs would be just fine, thank you. Do the Altera
> Cyclone parts have something like this?

- DS


"Phil Hays" <SpamPos...@attbi.com> wrote in message
news:3D913E3F...@attbi.com...

Jack

unread,
Sep 25, 2002, 9:40:06 AM9/25/02
to
Sounds like you're being defensive, Austin. Announcing product before
it is available? Xilinx does this all the time. When did you first
start talking about Virtex-II Pro? I think I saw articles about two
years ago. I don't think this is a bad thing, necessarily. It is nice
to know what is coming in advance; design cycles are shorter in FPGAs
but they still aren't instantaneous.

However, what about the 2V1500 I was told would be available by June
(2001)? I think it just came out this August (2002). This is a
little more design time than was necessary, don't you think?
-Especially if you were counting on that June'01 delivery. I believe
this was also the case with the 2V2000.

http://www.xilinx.com/prs_rls/vtx2ship.htm
"The first members of the Virtex-II family... are sampling now with
the rest the family sampling by mid 2001."

Jack

rickman

unread,
Sep 25, 2002, 10:06:00 AM9/25/02
to
Jim Granville wrote:
>
> Package alone is not likely to be a dominant cost factor :
> Far more relevent, will be die area, yield, testing times, FAB run
> volumes,
> ( mask amortise) plus the M Squared fudge factor ( M^2 = Marketing
> Margin )
>
> ( see also other thread on higher end CPLD price-kick )

No, of course the package is not the only cost determining factor. But
smaller designs are often IO limited and a larger die must be purchased
in order to get the higher IO count.


> That said, it makes sound sense to offer a broad range of die in
> a common package - designs NEVER get smaller as they mature :)

Unfortunately in the low cost series of chips, the range of die in a
package is often limited. It seems the manufacturers incur costs based
on the number of line items on their price list. So they keep that to a
minimum on the low cost devices.

Personally, I don't see that. I view it more like the car manufacturers
do. Each factory needs to make a given number of units a year and can
make many different models. The cost of handling the models is low
compared to the cost of running the factory, so have lots of variations
on the theme as long as you can produce it on the same line.


> A good example, that proves this can be done, is the Actel ProASIC
> - they offer ALL die, from 75K to 1000K, in a PQFP208 package ( 7 steps
> ).
>
> If you really need IO, they also have a FBGA1152 on the biggest device.

Ah yes, but that is buying a lot of logic (or is it routing and the
logic is free?) to get the IOs. Another poster was saying he didn't
want to buy the IO to get the logic :)

Austin Lesea

unread,
Sep 25, 2002, 10:37:42 AM9/25/02
to
Jack,

Some parts come out quickly, others less so. Most of that is driven by market forces (where are the orders coming from?).

If you want a 2V1500, you can use the 2V2000 (or 2V3000) until the 2V1500 is ready. I am sure that our sales partners would arrange something
to make it worth your while.

Part of our success is having a wide range of parts that overlap in package and IO so that customers can optimize their choice of part once
they get into production.

The announcement of the agreement with IBM, the licensing of the Mindspeed serdes, the 405PPC(tm IBM), etc. all make for good press. The
rollout of the Virtex II Pro to the first beta customers happened roughly 12 weeks before the silicon was due to fab out. That way folks
could start designing in the product. The rollout of the technology makes it seem like the parts were announced, but that is linked to the
first datasheet that gets posted, not when we talk about .13u core technology (1/31/02 date on datasheet, ES parts shipped in March, 2002).

To announce a product 6 months before it gets here is just fine. If you can deliver. I do congratulate Altera on their delivery of Stratix,
which was on time, and maybe a little bit ahead of time for the first sample. Good work. Sometimes it all comes together.

Now comes the hard part: all of the family members that follow.

I intend to be accurate, and fair (and use facts). As for defensive? Absolutely. Part of a good defense is a good offense, as well. And
introducing Virtex II Pro and then extending the family to some 10 devices sounds pretty good to me (2Vp2 to 2VP100).

Austin

Jay

unread,
Sep 25, 2002, 11:40:47 AM9/25/02
to
The package is a really a small part of the cost of these chips. The
die are very large (and hence the circumfrence and associated I/O
ring), so I/O is cheap and easy to add, so they do. A smaller package
pin count, while technically producable, may only reduce the cost a
few percent. In contrast, on a small high yield die, package cost can
be a big part of the cost, but we're in the opposite end of the
spectrum with FPGAs.

So if the cost is nearly the same for a high or low I/O package, the
only advantage is ease of assembly for a larger pitch part. Products
that use FPGAs tend to be low volume, high value, so theres not much
pressure to have a lower tech soldering process either.

So these are some of the reasons people end up doing like use and
using 40% of the pins in an 1152 pin package.

John_H

unread,
Sep 25, 2002, 1:41:03 PM9/25/02
to
Keep in mind that the lower-cost devices such as the Spartan-IIE (and the
Cyclone?), the package *is* a significant portion of the overall cost, not
single digit percent. In the enormous xc2v6000, it's hard to imagine how
any package would impact the price.

I've been buying the bigger devices for pin count with low logic utilization
in my current designs compared to the telecom centric stuff I was doing a
few years back where I/O wasn't a big concern.

It takes all kinds...

Nicholas C. Weaver

unread,
Sep 25, 2002, 2:24:44 PM9/25/02
to
In article <3D91F52F...@mail.com>, John_H <johnha...@mail.com> wrote:
>Keep in mind that the lower-cost devices such as the Spartan-IIE (and the
>I've been buying the bigger devices for pin count with low logic utilization
>in my current designs compared to the telecom centric stuff I was doing a
>few years back where I/O wasn't a big concern.

One observation is that they are still using perimiter pads on these
parts, so that upping the IO beyond a certain point necessitates a
bigger die.

I'd personally like to see an area pad FPGA, where some of the logic
blocks are replaced with pads, so we wouldn't have these issues.

Marc Randolph

unread,
Sep 25, 2002, 10:21:08 PM9/25/02
to
John_H <johnha...@mail.com> wrote in message news:<3D91F52F...@mail.com>...

> Jay wrote:
>
> > The package is a really a small part of the cost of these chips. The
> > die are very large (and hence the circumfrence and associated I/O
> > ring), so I/O is cheap and easy to add, so they do. A smaller package
> > pin count, while technically producable, may only reduce the cost a
> > few percent. In contrast, on a small high yield die, package cost can
> > be a big part of the cost, but we're in the opposite end of the
> > spectrum with FPGAs.
> >
> > So if the cost is nearly the same for a high or low I/O package, the
> > only advantage is ease of assembly for a larger pitch part. Products
> > that use FPGAs tend to be low volume, high value, so theres not much
> > pressure to have a lower tech soldering process either.
> >
> > So these are some of the reasons people end up doing like use and
> > using 40% of the pins in an 1152 pin package.
> >
>
> Keep in mind that the lower-cost devices such as the Spartan-IIE (and the
> Cyclone?), the package *is* a significant portion of the overall cost, not
> single digit percent. In the enormous xc2v6000, it's hard to imagine how
> any package would impact the price.
>
> I've been buying the bigger devices for pin count with low logic utilization
> in my current designs compared to the telecom centric stuff I was doing a
> few years back where I/O wasn't a big concern.
>
> It takes all kinds...
>

Indeed it does. This discussion has been quite interesting to me -
we've heard from people from all corners of the spectrum.

For the record, although the cost incurred in going with the larger
package is a factor, by far the bigger factor in going with a larger
package is the area it takes up. The FG676 package is the best
compromise in area and pin density of any of the packages, in my
opinion. We simply don't have room for the larger packages, but we
would sure be willing to pay for more LUT's in the FG676 package...

Have fun,

Marc

Marc Randolph

unread,
Sep 26, 2002, 5:58:17 PM9/26/02
to
kayr...@yahoo.com (Jay) wrote in message news:<d049f91b.02092...@posting.google.com>...

> The package is a really a small part of the cost of these chips.
[... snip rest ...]

I guess it all depends on what you consider to be "small."

To get more LUTs than is in an XC2V3000, the only package offered is a
flip-chip. That's a 20% price hike (I just verified this). Add that
to the fact it takes up 70% more area, and you have the reason that I
can't make that move.

Have fun,

Marc

Hal Murray

unread,
Sep 28, 2002, 1:44:10 AM9/28/02
to
>One observation is that they are still using perimiter pads on these
>parts, so that upping the IO beyond a certain point necessitates a
>bigger die.

>I'd personally like to see an area pad FPGA, where some of the logic
>blocks are replaced with pads, so we wouldn't have these issues.

I haven't thought about that apporach. Is there a web site or
paper that gives a good overview?

I assume one problem would be inductance in the bonding wires.
That could make placement "interesting" to say the least.

Or can they do a micro-BGA onto a ceramic substrate and turn
that into super-short bond wires?


--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

Pete Ormsby

unread,
Sep 28, 2002, 8:54:25 AM9/28/02
to

Nicholas C. Weaver <nwe...@ribbit.CS.Berkeley.EDU> wrote in message
news:amsv1c$4nr$1...@agate.berkeley.edu...

> One observation is that they are still using perimiter pads on these
> parts, so that upping the IO beyond a certain point necessitates a
> bigger die.
>
> I'd personally like to see an area pad FPGA, where some of the logic
> blocks are replaced with pads, so we wouldn't have these issues.
> --

The Altera Mercury devices have I/O pads located throughout the middle of
the device as well as around the perimeter. Look at the floorplan of the
device and you'll see I/O running in rows straight through the part.
However, it seems that the reason for this I/O structure was performance,
rather than a greater I/O-per-die-area ratio.

-Pete-


Steve Mensor

unread,
Sep 28, 2002, 1:32:31 PM9/28/02
to
I think product availability for new product introductions is an
excellent topic for discussion. Often new semiconductor technology can
be the vehicle for system companies to create new products with
competitive and differentiating advantages. The downside is the
possibility that the new semiconductor technology will not be
available when committed.

Altera is conscious of this issue and has done what it can to reduce
the risk of product delays. The first thing that we did was add the
product availability schedule to our web site so customers can get the
rollout schedule for Stratix at anytime:
http://www.altera.com/products/devices/stratix/overview/stx-overview.html.
Second, we are more conservative with our shipment dates to give time
to fix any problems if they arise with the new silicon. With Stratix,
things have gone very well and we have been able to beat the published
schedule for most of the devices. By the end of next week we will have
sampled 5 members from the Stratix family: 1S10, 1S20, 1S25, 1S40 and
1S80. Additionally, we have pulled in the availability of the fastest
speed grade devices, which are available now, and we pulled in the
transition from ES to production, which will be next week for the
1S25. We will not be able to always beat our schedules, but as a rule
of thumb we should always meet our published schedule.

As for Cyclone, we feel very confident that it will roll-out on time.
We are using the same proven process that is being used for Stratix
and for the 2A70 in the APEX II family -- a process that has been in
production for almost a year. The die size for Cyclone devices are
quite small and there is no new exotic technology incorporated. The
schedules have not been published to our web site yet, but we plan to
do that in the next 2 weeks. Currently, we expect to start shipping
the 1C20 in January and 1C6 in February. The remaining 2 devices will
be available in April.

I hope this is useful.

Thanks,
Steve Mensor

Reply all
Reply to author
Forward
0 new messages