Google Groups no longer supports new Usenet posts or subscriptions. Historical content remains viewable.
Dismiss

Virtex 5 ISERDES

7 views
Skip to first unread message

maxascent

unread,
Nov 23, 2009, 6:47:48 AM11/23/09
to
I am looking at using the ISERDES block in a V5 design for a DDR2
controller. I want to input the DQ into an IODELAY block and then into the
ISERDES. Problem is I am not sure that you can do this anymore. I have seen
some old app notes with this configuration and a DDLY input on the ISERDES.
But the new user guides dont have this input and they call the ISERDES a
NODELAY block. Does anyone know anymore info regarding this?

Jon

---------------------------------------
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

maxascent

unread,
Nov 23, 2009, 8:27:26 AM11/23/09
to
It looks like you can use the ISERDES with an IODELAY but you have to
instantiate a Virtex 4 ISERDES not the Virtex 5 ISEDES_NODELAY. Just tried
it with ISE and it mapped and p&r ok.
Message has been deleted

maxascent

unread,
Nov 24, 2009, 3:56:42 AM11/24/09
to
What kind of race conditions?
MIG is ok but I would rather have my own so I can be sure what its doing.
0 new messages