Virtex 5 GC clock pin vs GC//CC clock pins

[Michael]

Hi,

What is the difference between a GC clock pin and a GC/CC clock pin(I
dont mean a CC pin I mean a GC/CC pin)?

Such as below for a V5 xc5vlx50t, package ff665,

AB14|adc2_dco_p|IOB|IO_L7P_GC_VRN_4|INPUT|LVDS_25|4||||NONE||LOCATED|NO|DIFF_TERM|
AB15|adc1_dco_p|IOB|IO_L9P_CC_GC_4|INPUT|LVDS_25|4||||NONE||LOCATED|NO|DIFF_TERM|

Any disadvantage with the GC/CC compared to a pure GC pin?

/michael

[Gabor]

I think this was answered in the Xilinx forums, but basically the GC pin
has dedicated routing to global resources (BUFGMUX, DCM, PLL) and the CC
pin has dedicated routing to local resources (BUFR, BUFIO). A GC_CC pin
would therefore have both capabilities. In the older series where local
clocking resources first showed up (Spartan 3E, 3A?) there was no
advantage to the local clocking if you already had the global
connections. In the newer parts, the local clocking can run faster
than the max toggle rate of the global routes, so there is some
advantage to adding the CC capability to a GC pin.

-- Gabor