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Xilinx Coregen 2.3 problem

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Vijayant

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May 29, 2007, 3:17:24 PM5/29/07
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Hi,
We are using FIFO in our design. The FIFO has been generated using
CoreGenerator 2.3. The programmable flags have been enabled. The
threshold values have been kept within the depth limit. However, when
we try to synthesize on Xilinx, we get warnings:
WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/
prog_empty_thresh_assert<9>' has no driver
WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/
prog_empty_thresh_assert<8>' has no driver
WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/
prog_empty_thresh_assert<7>' has no driver
WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/
prog_empty_thresh_assert<6>' has no driver
WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/
prog_empty_thresh_assert<5>' has no driver
WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/
prog_empty_thresh_assert<4>' has no driver
WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/
prog_empty_thresh_assert<3>' has no driver
WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/
prog_empty_thresh_assert<2>' has no driver
WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/
prog_empty_thresh_assert<1>' has no driver
WARNING:NgdBuild:452 - logical net 'fifo1/fifo1/BU2/
prog_empty_thresh_assert<0>' has no driver

Similar warnings are got for 'prog_empty_thresh_assert',
'prog_full_thresh_negate', 'prog_full_thresh',
'prog_empty_thresh_negate', 'prog_empty_thresh',

Secondly, our top level entity of the FIFO generated by Coregen does
not have signals labeled rd_clk and wr_clk. Still we got the following
errors :

Vijayant

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May 29, 2007, 3:19:03 PM5/29/07
to

NgdBuild:452 - logical net 'fifo1/fifo1/BU2/rd_clk' has no driver
NgdBuild:452 - logical net 'fifo1/fifo1/BU2/wr_clk' has no driver

Pls help.

Regards,
Vijayant

Vijayant

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May 30, 2007, 1:14:29 PM5/30/07
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Hi Gurus,
I need help desperately. Please help.

Regards,
Vijayant

John_H

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May 30, 2007, 1:40:40 PM5/30/07
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"Vijayant" <vijayant....@gmail.com> wrote in message
news:1180466343.2...@p77g2000hsh.googlegroups.com...

Can you find the instantiation of BU2 in your code? You'll need to have
ports on BU2 of rd_clk, wr_clk, and prog_empty_thresh_assert. I can't
comment on why this aren't connected in the coregen output according to your
flow, only that there are ports (according to the software) and they don't
appear to be connected (in BU2, according to the software).

Good luck on this very basic level of "looking at your code."


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